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US 6,611,010 B2Granted
Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsAkira Goda, Kazuhiro Shimizu, Yuji Takeuchi, Riichiro Shirota, Seiichi Aritome
Life of this patent
Estimating the term…
Abstract
In a bit line contact section, a contact hole is formed through a silicon oxide film, and a contact plug made of a polysilicon film doped with impurities is buried in the contact hole. The silicon oxide film is formed with a wiring groove overlapping the contact hole. A bit line made of a metal film is buried in the wiring groove. The contact plug extends through the bit line, and has its upper surface substantially coplanar with an upper surface of the bit line. The contact plug is in contact with the bit line only on its side surfaces.
Claims55
A semiconductor device comprising:
- a contact plug arranged in a contact hole and having an upper portion protruding from said contact hole;
- and
- a wiring in contact with said contact plug, said wiring being made of a material different from a material of which said contact plug is made,
- wherein said contact plug extends through said wiring, and said contact plug has an upper surface substantially coplanar with an upper surface of said wiring.
1 more element
A semiconductor device comprising:
- an element isolation area;
- an element area surrounded by said element isolation area;
- and
- a metal film arranged on said element area, said metal film having end portions arranged in a contact hole overlapping said element isolation area and in a wiring groove on said contact hole.
1 more element
A semiconductor device comprising;
- a bit line contact plug for connecting a diffusion layer of a memory cell to a bit line;
- a word line contact plug connected to a word line;
- a gate contact plug connected to a gate electrode of a MOS transistor in a peripheral circuit section;
- a diffusion layer contact plug connected to a diffusion layer of said MOS transistor;
- and
- a well contact plug connected to a well region,
- wherein said bit line contact plug is made of the same material as at least one of said word line contact plug, said gate contact plug, said diffusion layer contact plug and said well contact plug.
4 more elements
A semiconductor device comprising;
- a bit line contact plug for connecting a NAND cell unit to a bit line;
- a source line contact plug for connecting said NAND cell unit to a source line;
- a word line contact plug connected to a word line;
- a first gate contact plug connected to a gate electrode of a MOS transistor in a peripheral circuit section;
- a second gate contact plug connected to a gate electrode of a select transistor in said NAND cell unit;
- a diffusion layer contact plug connected to a diffusion layer of said MOS transistor;
- and
- a well contact plug connected to a well region,
- wherein said bit line contact plug, said source line contact plug, said word line contact plug, said first gate contact plug, said second gate contact plug, said diffusion layer contact plug and said well contact plug are formed of the same material.
6 more elements
A semiconductor device comprising:
- element isolation areas;
- first and second element areas sandwiched by said element isolation areas;
- a first contact plug connected to said first element area, said first contact plug having an end portion overlapping said element isolation areas;
- and
- a second contact plug connected to said second element area, said second contact plug having an end portion not overlapping said element isolation areas,
- wherein said first and second contact plugs are formed of the same material.
3 more elements
A non-volatile semiconductor memory device comprising:
- element areas and element isolation areas repeatedly arranged in a first direction at a regular period;
- memory cells arranged in said element areas;
- contact holes arranged in said first direction at the same period as said regular period;
- and
- a wiring arranged in said contact holes for communicating data with said memory cells,
- wherein said contact holes have a width in a second direction orthogonal to said first direction larger than a width of said contact hole in said first direction.
3 more elements
A non-volatile semiconductor memory device comprising:
- element areas and element isolation areas repeatedly arranged in a first direction at a regular period;
- memory cells arranged in said element areas;
- first contact holes arranged in said first direction substantially at the same period as said regular period;
- a bit line arranged in said first contact holes, said bit line connected to one end of a current path of each said memory cell through at least one transistor;
- second contact holes arranged in said first direction substantially at the same period as said regular period;
- and
- a source line arranged in said second contact holes, said source line connected to the other end of the current path of each said memory cell through at least one transistor,
- wherein both said first and second contact holes have a width in a second direction orthogonal to said first direction larger than a width in said first direction.
5 more elements
A nonvolatile semiconductor memory device comprising:
- element areas and element isolation areas, which are arranged at regular intervals in a first direction;
- memory cells arranged in the element areas, respectively;
- contact plugs arranged at the same intervals as the regular intervals in the first direction, and connected to the element areas, respectively;
- and
- wirings connected to the contact plugs, and formed of material different from material of the contact plugs,
- wherein upper surfaces of the contact plugs are located at a higher level than lower surfaces of the wirings.
3 more elements
A nonvolatile semiconductor memory device comprising:
- element isolation areas;
- an element area provided between the element isolation areas;
- and
- a contact plug connected to the element area,
- wherein an end portion of the contact plug overlaps the element isolation areas, and
- the contact plug is made of metal material.
3 more elements
A nonvolatile semiconductor memory device comprising:
- element areas and element isolation areas, which are arranged at regular intervals in a first direction;
- memory cells and selection-transistors, which are arranged in the element areas, respectively;
- and
- contact plugs arranged in the first direction at intervals which are substantially equal to the regular intervals, and contacting the element areas, respectively,
- wherein:
- the contact plugs are bit line contacts connected to one end of current paths of the memory cells through the selection-transistors;
- portions of the contact plugs overlap the element isolation areas;
- respectively, and
- the contact plugs are made of metal material.
6 more elements
Dependencies are inferred from the claim text.