Vertical component peripheral structure
AssigneeSTMicroelectronics S.r.l.
InventorMathieu Roy
Life of this patent
Estimating the term…
Abstract
A power component formed in an N-type silicon substrate, the lower and upper surfaces of which respectively include a first and a second P-type region that do not extend to the component periphery, a high voltage being capable of existing between the first and second regions and having to be withstood by the junctions between the first and second regions and the substrate. A deep insulating region that does not join the first region is provided at the lower periphery of the component, the lower surface of the substrate between said deep insulating region and the first region being coated with an insulating layer, the height of the deep insulating region being greater than that of a possible soldering upward extension formed during the soldering of the lower surface on a heat sink.
Claims26
A power component formed in a silicon substrate of a first conductivity type, lower and upper surfaces of which respectively include a first and a second region of the second conductivity type that do not extend up to a periphery of the component, a high voltage being capable of existing between the first and second regions and having to be withstood by junctions between the first and second regions and the substrate,
- including an insulating region, formed in the lower surface of the substrate at the periphery of the component without joining the first region, the lower surface of the substrate between said insulating region and the first region being coated with an insulating layer, a height of the insulating region being greater than that of a soldering upward extension formed during the soldering of the lower surface on a heat distributor.
A power component comprising:
- a silicon substrate of a first conductivity type;
- a first region of a second conductivity type disposed in the silicon substrate at a first surface of the silicon substrate;
- a second region of the second conductivity type disposed in the silicon substrate at a second surface of the silicon substrate;
- and
- an insulating region disposed in the silicon substrate at a periphery of the silicon substrate such that a portion of the silicon substrate separates the insulating region from the first region and the second region, the insulating region being arranged to provide isolation between the first and second regions and a solder extension disposed at the periphery of the silicon substrate.
A power component comprising:
- a silicon substrate of a first conductivity type;
- a first region of a second conductivity type disposed in the silicon substrate at a first surface of the silicon substrate;
- a second region of the second conductivity type disposed in the silicon substrate at a second surface of the silicon substrate;
- a means for creating a space charge area adjacent to the first region and delimited by a first equipotential surface and second equipotential surface, the second equipotential surface being of higher potential that the first equipotential surface;
- and
- an insulating region disposed at the second surface of the silicon substrate that prevents leakage currents and short circuiting between first and second equipotential surfaces.
A power component comprising:
- a silicon substrate of a first conductivity type;
- a first region of a second conductivity type disposed in the silicon substrate at a first surface of the silicon substrate;
- a second region of the second conductivity type disposed in the silicon substrate at a second surface of the silicon substrate;
- and
- an insulating region dispose in the silicon substrate such that a portion of the silicon substrate separates the insulating region from the first region, the insulating region being arranged to protect against an alteration of a breakdown voltage of the power component and against a short-circuiting of the power component caused between either of the first and second regions and a soldering extension.
Dependencies are inferred from the claim text.