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AssigneeNintendo Co., Ltd.
InventorsDan Shimizu, Genyo Takeda, Ko Shiota, Munehito Oira, Kazuo Koshima, Satoshi Nishiumi
Estimating the term…
An advantageous set of external interfaces for home video game platform provide modularity and expandability while maintaining and preserving the proprietary nature of the platform. A disk drive interface provides flexible communications with an internal disk drive. Various serial bus interfaces provide expandability and interconnectability with a variety of internal and external devices including, for example, flash memory, broadband adapters, modems, and various other devices. A 4-port game controller interface provides serial interconnectability with handheld game controllers and various other input/output device. Power supply, digital and analog audio/video connections, and parallel memory expansion connections are also provided.
A gaming peripheral configured for connection to one of a plurality of interfaces of a home video game system of a type which provides external access to a first high potential terminal, a first ground terminal for the first high potential terminal, a second high potential terminal, a second ground terminal for the second high potential terminal, and four other ground terminals, and to a serial data line, wherein one or more of the interfaces also provides external access to a latch signal line and wherein the serial data lines and the latch signal lines of the interfaces connect via isolation buffers to a serial bus coupled to a graphics and audio processor of the home video game system, said gaming peripheral including:
A gaming communication device configured for connection to an interface of a home video game system of a type which provides external access to a first high potential terminal, a first ground terminal coupled to the first high potential terminal, a second high potential terminal, and a second ground terminal coupled to the second high potential terminal and to a bus connected to a graphics and audio processor of the home video game system which includes a device insertion status signal line, a data output line having a first uni-directional output buffer controlled by a signal on the device insertion status signal line, a clock signal line having a second uni-directional output buffer controlled by the signal on the device insertion status signal line, a chip select signal line having a third uni-directional output buffer controlled by the signal on the device insertion status signal line, a data input line having a uni-directional input buffer controlled by a signal on the chip select signal line, an interrupt signal line, said gaming communication device comprising:
A gaming communication device configured for connection to an interface of a home video game system provided in a recess formed in a surface of the home video game system, the interface being of a type which provides external access to a first high potential terminal, a first ground terminal coupled to the first high potential terminal, a second high potential terminal, and a second ground terminal coupled to the second high potential terminal and to a bus connected to a graphics and audio processor of the home video game system which includes a device insertion status signal line, a data output line having a first uni-directional output buffer controlled by a signal on the device insertion status signal line, a clock signal line having a second uni-directional output buffer controlled by the signal on the device insertion status signal line, a chip select signal line having a third uni-directional output buffer controlled by the signal on the device insertion status signal line, a data input line having a uni-directional input buffer controlled by a signal on the chip select signal line, an interrupt signal line, said gaming communication device comprising:
A gaming peripheral device configured for connection to an interface of a home video game system, wherein the interface provides access to a processing system of the home video game system and comprises a data bus, a data direction signal line for a direction signal that controls the direction of data on the data bus, a host strobe signal line for a host strobe signal that qualifies output data on the data bus, a device strobe signal line for a device strobe signal that qualifies input data on the data bus, an error signal line for an error signal indicative of a gaming peripheral device error, a break signal line for a break signal that interrupts a command for the gaming peripheral device, a position signal line for a position signal indicative of a position of a mechanical component of the gaming peripheral device and a reset signal line for a reset signal for the gaming peripheral device, the gaming peripheral device comprising:
A gaming peripheral device configured to connect to an interface of a home video game system, wherein the interface provides access to a processing system of the home video game system and comprises a high level potential terminal, an input signal fine normally at a low level state, serial data out line, a serial data in line, a select signal line, a clocking signal line, and an interrupt signal line, and wherein the home video game system detects that the gaming peripheral device is connected to the interface when the potential of the input signal line becomes a high level state, the gaming peripheral device comprising:
A memory device configured to connect to an interface of a home video game system, wherein the interface provides access to a processing system of the home video game system and comprises a first high level potential terminal, a second high level potential terminal, a low level potential terminal, an input signal line normally at a low level state, a serial data out line, a serial data in line, a select signal line, a clocking signal line, and an interrupt signal line, and wherein the home video game system detects that the memory device is connected to the interface when the potential of the input signal line becomes a high level state, the memory device comprising:
Dependencies are inferred from the claim text.