US 6,609,244 B2Granted

Design method of a logic circuit

AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.

InventorsNaoki Kato, Kazuo Yano, Hidetoshi Chikata, Shunzo Yamashita

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Abstract

Even if only logic circuits described in HDL are distributed over a network, if the logic synthesis ability is insufficient, the overall design capability cannot be enhanced; e.g., a sufficient performance of a gate level logic circuit cannot be attained, or it takes a long time to complete logic synthesis. Considering design skills for logic synthesis are considered as property, the invention enables distribution of design skills between a plurality of design sites over a network interconnecting computers. Charges for a design skill are set for the rates of improvement to the performance of the logic circuit that was refined by the design skill. Desired circuit performance can be attained in a shorter period by shortening the design phases in which an RTL logic circuit is supplied as input and by logic synthesis thereon, a gate level logic circuit is output.

Claims7

Dependent claims

The A logic circuit design method in which a logic circuit on a register transfer level or a behavior level, generated at a first site, is transferred to a second site at which logic synthesis on the circuit is performed, comprising:

receiving a first logic circuit on the register transfer level or behavior level and a second logic circuit on a gate level output from logic synthesis executed on said first site by using a first library and under synthesis constraints for said first logic circuit, sent from said first site;
evaluating said second logic circuit performance and confirming that evaluated performance agrees with the performance of said second logic circuit evaluated on said first site;
generating a third logic circuit on the gate level by executing logic synthesis on said first logic circuit, using said first library and under the synthesis constraints for said first logic circuit;
evaluating said third logic circuit performance and evaluating performance improvement by comparing the third logic circuit performance with the second logic circuit performance which was evaluated and confirmed as the agreed one;
and
sending said third logic circuit and information on the performance improvement to said first site;
wherein a party at said second site receives a design charge which is set, depending on the performance improvement from a party at said first site.

4 more elements

A logic circuit design in which a logic circuit on a register transfer level or a behavior level, generated at first site, is transferred to a second site at which logic synthesis on the circuit is performed, said first and second sites being connected by a network so that information can be transferred therebetween, comprising:

receiving said first logic circuit on the register transfer level or behavior level sent over said network from said first site;
generating a second logic circuit by executing logic synthesis on said first logic circuit, using a first library employed at said first site and under synthesis constraints for said first logic circuit;
evaluating said second logic circuit performance and evaluating performance improvement by comparing the evaluated performance of said second logic circuit with the evaluated performance of a gate level logic circuit output from logic synthesis on said first logic circuit, executed on said first site, by employing said first library;
and
sending said second logic circuit and information on the performance improvement over said network to said first site;
wherein a party at said second site receives a design charge which is set, depending on the performance improvement from a party at said first site.

3 more elements

Dependencies are inferred from the claim text.