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US 6,609,243 B1Granted
Layout architecture to optimize path delays
AssigneeCypress Semiconductor Corporation
InventorsBrian P. Evans, Jeffery Scott Hunt
Life of this patent
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Abstract
An apparatus comprising a first stage and a second stage. The first stage may comprise a first section and a second section. The second stage may be embedded between the first and second sections. The first and second stages may be configured to equalize signal paths between a plurality of inputs of the first stage and a plurality of outputs of the second stage.
Claims18
An apparatus comprising:
- a first stage comprising a first section and a second section;
- and
- a second stage between said first and second sections, wherein said first and second stages are configured to equalize signal paths between a plurality of inputs of said first stage and a plurality of outputs of said second stage, wherein said first and second sections are further configured to couple longer stage-to-stage connections to shorter routes of said outputs.
An apparatus comprising:
- means for providing a first stage comprising a first section and a second section;
- means for implementing a second stage between said first and second sections;
- and
- means for equalizing signal paths between a plurality of inputs of said first stage and a plurality of outputs of said second stage, wherein said first and second sections are further configured to couple longer stage-to-stage connections to shorter routes of said outputs.
1 more element
A method for optimizing delay paths, comprising the steps of:
- (A) providing a first stage comprising a first section and a second section;
- (B) implementing a second stage between said first and second sections;
- and
- (C) equalizing signal paths between a plurality of inputs of said first stage and a plurality of outputs of said second stage and routing said inputs to said outputs.
1 more element
Dependencies are inferred from the claim text.