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US 6,609,241 B2Granted
Method of designing clock wiring
AssigneeNEC Corporation
InventorShigeki Yonemori
Life of this patent
Estimating the term…
Abstract
A delay model of a macro is prepared in advance, and a delay of a top level is calculated using the delay model, to thereby reduce the clock skews between the respective macros to which clocks are supplied, within a functional block being designed.
Claims28
A method of designing a wiring comprising:
- classifying a functional block into a top level and a macro, said top level being at a higher level than said macro;
- arranging a top level wiring connecting said top level and said macro;
- providing a delay model of said macro;
- calculating a delay between said top level and said macro based on said delay model;
- and arranging a macro wiring in said macro based on said delay;
- wherein said macro comprises a first macro and a second macro, and wherein the step of providing a delay model comprises providing a first delay model corresponding to said first macro and providing a second delay model corresponding to said second macro;
- defining an output terminal of said top level that outputs a signal to said first macro and said second macro, wherein the step of calculating a delay between said top level and said macro further comprises calculating a first delay for a path between said output terminal and said first macro and a second delay for a path between said output terminal and said second macro, the calculating of first and second delays being based on said first delay model and said second delay model.
4 more elements
A method of designing wiring for a semiconductor device comprising:
- providing a cock terminal, a first functional block and a second functional block, said clock terminal and said first and second functional blocks being apart from one another, said clock terminal being applied with a clock signal, said first functional block having a first input terminal and a first cell, said second functional block having a second input terminal and a second cell;
- providing a first wiring connection between said clock terminal and said first input terminal and a second wiring connection between said clock terminal and said second input terminal;
- providing in said first function block a first buffer having an input end connected to said first terminal and in a second functional block a second buffer having an input end connected to said second input terminal;
- calculating a first propagation delay of said clock signal through said first wiring connection nd a second propagation delay of said clock signal through said second wiring connection;
- and arranging said first and second cells respectively in said first and second functional block to connect said first and second cells respectively to output ends of said first and second buggers such that a skew between said first and second propagation delays may be eliminated at said first and second cells.
2 more elements
Dependencies are inferred from the claim text.