Efficient integrated circuit layout for improved matching between I and Q paths in radio receivers
AssigneeNational Semiconductor Corporation
InventorBernard Xavier
Life of this patent
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Abstract
An integrated circuit is disclosed that provides improved matching between I and Q paths in radio receiver circuits. The integrated circuit comprises at least one circuit element that is divided into a first half strength circuit element located in a first area of a module and a second half strength circuit element located in a second area of the module. The first and second areas are oppositely located with respect to a central area of the module and minimize component mismatch by averaging out process gradients within the module. Methods for laying out the circuit elements of the integrated circuit are also disclosed.
Claims20
A method for placing circuit elements within an integrated circuit comprising the steps of:
- dividing at least one circuit element of said integrated circuit into a first half strength circuit element and a second half strength circuit element;
- placing said first half strength circuit element in a first area of a module of said integrated circuit;
- placing said second half strength circuit element in a second area of said module of said integrated circuit;
- wherein said first area and said second area are oppositely located with respect to a central area of said module of said integrated circuit.
A method for placing circuit elements within an integrated circuit of the type comprising an in-phase (I) path and a quadrature (Q) path, said method comprising the steps of:
- dividing at least one I path circuit element of said integrated circuit into a first I path half strength circuit element and a second I path half strength circuit element;
- dividing at least one Q path circuit element of said integrated circuit into a first Q path half strength circuit element and a second Q path half strength circuit element;
- placing said first I path half strength circuit element in a first area of a module of said integrated circuit;
- placing said second I path half strength circuit element in a second area of said module of said integrated circuit;
- wherein said first area and said second area are oppositely located with respect to a central area of said module;
- placing said first Q path half strength circuit element in a third area of said module of said integrated circuit;
- placing said second Q path half strength circuit element in a fourth area of said module of said integrated circuit;
- wherein said third area and said fourth area are oppositely located with respect to a central area of said module of said integrated circuit.
A method for minimizing component mismatch between circuit elements within an integrated circuit in which it is desired to match a first signal path and a second signal path, said method comprising the steps of:
- dividing at least one circuit element in said first signal path of said integrated circuit into a first half strength circuit element and a second half strength circuit element;
- placing said first half strength circuit element in a first area of a module of said integrated circuit;
- placing said second half strength circuit element in a second area of said module of said integrated circuit;
- wherein said first area and said second area are oppositely located with respect to a central area of said module;
- and
- wherein said opposite locations of said first area and of said second area average out at least one process gradient of said module.
An integrated circuit comprising at least one circuit element that is divided into a first half strength circuit element and a second half strength circuit element;
- wherein said first half strength circuit element is located in a first area of a module of said integrated circuit;
- wherein said second half strength circuit element is located in a second area of said module of said integrated circuit;
- and
- wherein said first area and said second area are oppositely located with respect to a central area of said module of said integrated circuit.
An integrated circuit of the type comprising an in-phase (I) path and a quadrature (Q) path, said integrated circuit comprising:
- at least one I path circuit element that is divided into a first I path half strength circuit element and a second I path half strength circuit element;
- at least one Q path circuit element that is divided into a first Q path half strength circuit element and a second Q path half strength circuit element;
- wherein said first I path half strength circuit element is located in a first area of a module of said integrated circuit;
- wherein said second I path half strength circuit element is located in a second area of said module of said integrated circuit;
- wherein said first area and said second area are oppositely located with respect to a central area of said module of said integrated circuit;
- wherein said first Q path half strength circuit element is located in a third area of said module of said integrated circuit;
- wherein said second Q path half strength circuit element is located in a fourth area of said module of said integrated circuit;
- and
- wherein said third area and said fourth area are oppositely located with respect to a central area of said module of said integrated circuit.
An integrated circuit having minimized component mismatch between circuit elements in which it is desired to match a first signal path and a second signal path, said integrated circuit comprising:
- at least one circuit element in said first signal path of said integrated circuit divided into a first half strength circuit element and a second half strength circuit element;
- wherein said first half strength circuit element is located in a first area of a module of said integrated circuit;
- wherein said second half strength circuit element is located in a second area of said module of said integrated circuit;
- wherein said first area and said second area are oppositely located with respect to a central area of said module of said integrated circuit;
- and
- wherein said opposite locations of said first area and of said second area average out at least one process gradient of said module of said integrated circuit.
Dependencies are inferred from the claim text.