Load sensitivity modeling in a minimal level sensitive timing abstraction model
AssigneeHewlett-Packard Development Company, L.P.
InventorsMartin Foltin, Brian Foutz, Sean Tyler
Life of this patent
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Abstract
A method for improved load sensitivity modeling in a minimal level sensitive timing abstraction model provides for an extension of the timing abstraction model. The timing abstraction model extension improves accuracy of the timing abstraction model by splitting setup/hold check nodes and/or dummy latch nodes at certain input and/or output ports.
Claims18
A method for providing improved load sensitivity modeling in a minimal level sensitive timing abstraction model modeling, comprising:
- extracting a plurality of parameters from a circuit that includes an input port and an output port;
- creating an echo-circuit that represents the plurality of parameters and models load sensitivity, wherein the echo-circuit is stimulus independent, port-based, has no internal latch nodes, and includes a check node at the input port and a dummy latch node at the output port, wherein the dummy latch nodes is controlled by an internally generated clock signal that becomes active when a latest clock signal from the circuit arrives at the output port, and wherein the echo-circuit enables a signal to propagate from the input port to the output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the output port;
- and
- splitting the check node at the input port into multiple check nodes, wherein the multiple check nodes correspond to multiple input logic elements.
A method for providing improved load sensitivity modeling in a minimal level sensitive timing abstraction model modeling, comprising:
- extracting a plurality of parameters from a circuit that includes an input port and an output port;
- creating an echo-circuit that represents the plurality of parameters and models load sensitivity, wherein the echo-circuit is stimulus independent, port-based, has no internal latch nodes, and includes a check node at the input port and a dummy latch node at the output port, wherein the dummy latch nodes is controlled by an internally generated clock signal that becomes active when a latest clock signal from the circuit arrives at the output port, and wherein the echo-circuit enables a signal to propagate from the input port to the output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the output port;
- and
- splitting the dummy latch node at the output port into multiple dummy latch nodes, wherein the multiple dummy latch nodes correspond to multiple output logic elements.
A computer readable medium providing instructions for providing improved load sensitivity modeling in a minimal level sensitive timing abstraction model, the instructions comprising:
- extracting a plurality of parameters from a circuit that includes an input port and an output port;
- creating an echo-circuit that represents the plurality of parameters and models load sensitivity, wherein the echo-circuit is stimulus independent, port-based, has no internal latch nodes, and includes a check node at the input port and a dummy latch node at the output port, wherein the dummy latch nodes is controlled by an internally generated clock signal that becomes active when a latest clock signal from the circuit arrives at the output port, and wherein the echo-circuit enables a signal to propagate from the input port to the output port only if the signal arrives at the output port later than a latest clock signal from any pin clock signal controlling the output port;
- and
- splitting the check node at the input port into multiple check nodes, wherein the multiple check nodes correspond to multiple input logic elements.
Dependencies are inferred from the claim text.