Apparatus and method for automatically verifying a designed circuit

An apparatus for automatically verifying a designed semiconductor integrated circuit specified in accordance with circuit information,

• wherein at least one verification symbol which specifies a node name and a verification content for a node to be verified in the circuit is inserted in advance into the circuit information of the semiconductor integrated circuit, and
• wherein the apparatus comprises:
• verification-condition extracting section for analyzing a circuit information including the verification symbol, and extracting the node name and verification content of the node to be verified;
• pattern generating section for generating a verification pattern to be used for verification from the extracted node name and verification content;
• and
• acceptance/rejection determining section for executing a circuit simulation by using the verification pattern, analyzing the simulation result, and determining whether the verified node is of acceptance or rejection.

A method of automatically verifying a designed circuit which is generated by a generator for generating a circuit diagram of a whole semiconductor integrated circuit in accordance with an arrangement of cells which are regarded as parts, each cell defining a predetermined circuit unit,

• wherein a verification symbol which specifies a node name and a verification content for a node to be verified is inserted in advance into at least one of the cells arranged as parts, and
• wherein the method comprises:
• analyzing a circuit diagram of the whole semiconductor integrated circuit generated in accordance with the arrangement of cells including at least one verification symbol, and extracting the node name and the verification content of the node to be verified;
• generating a verification pattern to be used for verification from the extracted node name and verification content;
• and
• executing a circuit simulation by using the verification pattern and then analyzing the simulation result to determine whether the verified node is of acceptance or rejection.

A method of automatically verifying a designed semiconductor integrated circuit specified in accordance with circuit information,

• wherein at least one verification symbol which specifies a node name and a verification content for a node to be verified in the circuit is inserted in advance into the circuit information of the semiconductor integrated circuit, and
• wherein the method comprises:
• analyzing a circuit information including the verification symbol, and extracting the node name and verification content of the node to be verified;
• generating a verification pattern to be used for verification from the extracted node name and verification content;
• and
• executing a circuit simulation by using the verification pattern and then analyzing the simulation result to determine whether the verified node is of acceptance or rejection.