US 6,609,229 B1 · Method for automatically generating checkers for finding functional defects in a description of a circuit

Abstract

A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers. Some of the checkers may use signals generated by other checkers.

Claims122

Dependent claims

A method for functional verification of a circuit, said method being implemented in a programmed computer, said method comprising:

converting a circuit description into a graph, said graph including a plurality of nodes and a plurality of connections among said nodes;
automatically examining said graph for a first instance of a first predetermined arrangement of said nodes and connections;
automatically generating first instructions that represent a first checker for flagging a first predetermined defective behavior of a first device represented in the circuit description;
simulating the behavior of said first device and of said first checker, wherein during simulation said first checker monitors signals to or from the first device for conformance with the first predetermined defective behavior;
automatically examining said graph for a second instance of a second predetermined arrangement;
and
automatically generating second instructions that represent a second checker for flagging a second predetermined defective behavior of a second device represented in the circuit description, said second instructions using a signal generated by said first instructions.

4 more elements

Dependencies are inferred from the claim text.

Method for automatically generating checkers for finding functional defects in a description of a circuit

Life of this patent

Method for automatically generating checkers for finding functional defects in a description of a circuit

Life of this patent

Abstract

Claims122