Latch clustering for power optimization

A method of clock optimization comprising:

• creating an initial placement of clock feeding circuits according to clock signal requirements;
• identifying clusters of said clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within said cluster is connected;
• and
• changing pin connections between said clock feeding circuits and clock signal supply devices to switch selected ones of said clock feeding circuits to different clusters to reduce lengths of wires between said clock feeding circuits and said clock signal supply devices within each cluster,
• wherein said changing is performed so as to minimize a cost function associated with moving said clock feeding circuits from an original clock feeding circuit location.

A program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform a method of clock optimization comprising:

• creating an initial placement of clock feeding circuits according to clock signal requirements;
• identifying clusters of said clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within said cluster is connected;
• and
• changing pin connections between said clock feeding circuits and clock signal supply devices to switch selected ones of said clock feeding circuits to different clusters to reduce lengths of wires between said clock feeding circuits and said clock signal supply devices within each cluster,
• wherein said changing is performed so as to minimize a cost function associated with moving said clock feeding circuits from an original clock feeding circuit location.