US 6,609,227 B2 · Scheduler for schematic related jobs

Abstract

A Schematic database defining a Schematic is checked and saved. Multiple programs affected by the Logic of the VLSI Schematic are launched along with a Checking program that extracts data related to the Logic of the VLSI Schematic design and other data that may be necessary but is not related to the Logic of the VLSI Schematic design. The Schematic design programs operate as executable program states with each program state having program data inputs and outputs and program logic inputs and outputs. Once the method is started, a designer simply corrects errors that occur and then restarts the Schematic design process. If changes in the Schematic database do not affect the Logic then Logic related programs states are stopped and programs for correcting non Logic related changes are run. Program output data may be conditional with errors or unconditional without errors depending on operational modes.

Claims55

Dependent claims

An Integrated Circuit (IC) Schematic design method having a set of Schematic design programs and an initial Schematic database of data describing a Schematic for an IC, said IC Schematic design method comprising the steps of:

(a) organizing said set of Schematic design programs as executable programs states;
(b) coupling said executable program states with a program scheduler;
(c) executing, in parallel, selected Logic program states from said set of Schematic programs states;
(d) executing a checking program state, said checking program state operable to detennine if changes to said Schematic database data are related to a logic functionality of said IC;
(e) completing said selected Logic program states and starting additional Logic program states unless stopped by said program scheduler;
(f) determining if all program states in said set of program states have completed successfully;
(g) correcting said Schematic database data by said designer if all programs have not completed successfully;
and
(h) repeating said method steps from step (c-g) in response to one or more designer control inputs, wherein said designer control inputs comprise a start program scheduler, a stop program scheduler, set Audit Mode, and set Non-Audit Mode.

6 more elements

A computer program product for an Integrated Circuit (IC) schematic design method having a set of Schematic design programs and an initial schematic database of data describing a schematic for an IC, said computer program product embodied in a machine readable medium, including programming for a processor, said computer program comprising a program of instructions for performing the program steps of

(a) organizing said set of Schematic design programs as executable programs states;
(b) coupling said executable program states with a program scheduler;
(c) executing, in parallel, selected Logic program states from said set of Schematic programs states;
(d) executing a checking program state, said checking program state operable to determine if changes to said Schematic database data are related to a logic functionality of said IC;
(e) completing said selected Logic program states and starting additional Logic program states unless stopped by said program scheduler;
(f) determining if all program states in said set of program states have completed successfully;
(g) correcting said Schematic database data by said designer if all programs have not completed successfully;
and
(h) repeating said method steps from step (c-g) in response to one or more designer control inputs, wherein said designer control inputs comprise a start program scheduler, a stop program scheduler, set Audit Mode, and set Non-Audit Mode.

6 more elements

A data processing system, comprising:

a central processing unit (CPU);
shared random access memory (RAM);
read only memory (ROM);
an I/O adapter;
a display adapter;
a display;
and
a bus system coupling devices internal to said CPU, said CPU operable to execute computer program product for an Integrated Circuit Schematic design method, said IC Schematic design having a set of Schematic design programs and an initial Schematic database of data describing said IC Schematic, said computer program product embodied in a machine readable medium, including programming for a processor, said computer program comprising a program of instructions for performing the program steps of:
(a) organizing said set of Schematic design programs as executable programs states;
(b) coupling said executable program states with a program scheduler;
(c) executing, in parallel, selected Logic program states from said set of Schematic programs states;
(d) executing a checking program state, said checking program state operable to determine if changes to said Schematic database data are related to a logic functionality of said Schematic design;
(e) completing said selected Logic program states and starting additional Logic program states unless stopped by said program scheduler;
(f) determining if all program states in said set of program states have completed successfully;
(g) correcting said Schematic database data by said designer if all programs have not completed successfully;
and
(h) repeating said method steps from step (c-h) in response to one or more designer control inputs, wherein said designer control inputs comprise a start program scheduler, a stop program scheduler, set Audit Mode, and set Non-Audit Mode.

14 more elements

Dependencies are inferred from the claim text.

Scheduler for schematic related jobs

Life of this patent

Scheduler for schematic related jobs

Life of this patent

Abstract

Claims55