Methods and circuitry for built-in self-testing of content addressable memories

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• and
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search;
• and
• a search port interface that receives only 1 bit of test data from the BIST controller, other bits being generated internally to the search port interface, so as to limit a number of required global wires.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search;
• and
• a BIST maintenance interface for communicating test data to the CAM core, the BIST maintenance interface having a capability to expand 2 bits of data from the BIST controller to a required width, the capability to expand being configured to limit a number of needed global wires.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• and
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search, wherein BIST testing of the BIST circuit does not generate matches on all rows in the CAM core so as to enable low-power BIST operation.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• and
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search, wherein the CAM core is a ternary CAM core that is capable of storing three states.

Content addressable memory (CAM) circuitry with BIST testing capabilities, comprising:

• a plurality of CAM cores;
• a plurality of BIST circuits coupled to each of the CAM cores;
• and
• a single BIST controller being capable of controlling BIST testing of each of the plurality of CAM cores.

A method for performing built-in self-test (BIST) testing on a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• and
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search and a BIST write on the CAM core at the same time.