Method and apparatus for inducing bus saturation during operational testing of busses using a pattern generator

Apparatus for use in a computer system having a first resource, a second resource and a bus connecting the first and second resources, a bus driver for generating bus signals on the bus and a bus receiver for receiving the bus signals after they have traversed the bus and for generating a received bit pattern from the received bus signals, the received bit pattern representing a time sequence of received bus signals, the apparatus for testing the bus, comprising:

• a test storage which holds a predetermined test bit pattern that represents a time sequence of bus signals;
• test logic which responds to the predetermined test pattern by controlling the bus driver to generate a time sequence of bus signals on the bus that the test bit pattern represents;
• and
• a comparator which compares the test bit pattern to a received bit pattern generated by the bus receiver in response to the time sequence of bus signals on the bus, the comparator detecting discrepancies indicating bus errors.

A method for testing a bus in a computer system, the method comprising:

• (a) storing a predetermined test bit pattern that represents a time sequence of bus signals;
• (b) generating a time sequence of bus signals on the bus that the test bit pattern represents;
• (c) receiving the time sequence of bus signals from the bus after the bus signals have traversed the bus, and generating a received bit pattern from the received bus signals, the received bit pattern representing a time sequence of received bus signals;
• and
• (d) comparing the test bit pattern to the received bit pattern and detecting discrepancies indicating bus errors.