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US 6,609,209 B1Granted
Method and apparatus for reducing the power consumed by a processor by gating the clock signal to pipeline stages
AssigneeIntel Corporation
InventorsVivek Tiwari, Vinod Sharma, Sivakumar Makineni, Suri B. Medapati
Life of this patent
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Abstract
A processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.
Claims25
A processor comprising:
- a pipeline having first and second stages;
- a shift register having first and second latches;
- and
- an interface circuit to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.
1 more element
A computer system comprising:
- a processor;
- a system clock to provide a clock signal to the processor;
- a power supply to supply power to the processor;
- a pipeline of the processor having a plurality of stages;
- a shift register having a plurality of latches, each latch being associated with one of the stages;
- and
- an interface circuit coupled to the pipeline and the shift register to provide the clock signal to each stage based, at least in part, on a bit to be stored in each stage's associated latch and to reduce the power supplied by the power supply by preventing the clock signal from being provided to each stage based, at least in part, on a bit to be stored in each stage's associated latch.
4 more elements
A method of operating a processor comprising:
- storing a bit in each of a plurality of latches of a shift register, each latch having an associated pipeline stage of a pipeline, each bit of each latch having associated data in the pipeline stage and indicating if the associated data is valid;
- and
- providing a clock signal to a pipeline stage if data in the stage is valid, as determined, at least in part, by its associated bit.
Dependencies are inferred from the claim text.