Secure program execution using instruction buffer interdependencies
AssigneeSun Microsystems, Inc.
InventorAlan Folmsbee
Life of this patent
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Abstract
A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU changes with respect to pipelined instruction routing. Logic on the CPU is able to route a subset of the register bits, and selects destination logic gates in the microprocessor in a manner consistent with a programmable instruction decoder. This in turn establishes an instruction buffer interdependency.
Claims31
A processor for processing securely executable computer programs adapted for execution exclusively on processors specifically adapted for the security of said computer programs, comprising:
- an instruction buffer for receiving code portions including register bits comprising instructions from a securely executable computer program, said instruction buffer including a predetermined plurality of bit locations in a predetermined format;
- and
- logic circuitry including a programmable instruction decoder enabling interpretation of instructions stored in said instruction buffer according to the predetermined format at said plurality of bit locations, said logic circuitry configured to route said register bits to subsequent bit locations according to a predetermined interdependency criterion.
A microprocessor for processing computer programs which are selectively operable on selected ones of individual microprocessors, comprising:
- a store for a key shared with a compiler, the key used by the compiler to encrypt standard instructions into encrypted instructions;
- and
- an instruction buffer which contains logic able to route a subset of register bits from any bit locations in the buffer to destination logic circuits which reach a programmable instruction decoder, the routing of the register bits controlled in accordance with the key.
Method of processing computer programs on a selected one of individual microprocessors, the method comprising:
- buffering a first set of instructions as register bits;
- providing an excess of register bits;
- executing the instructions;
- buffering further instructions as register bits;
- and
- providing a verification of said first set of instructions and said further instructions conforming to a predetermined criteria.
A microprocessor for processing computer programs selectively operable on selected ones of individual microprocessors, comprising:
- at least one memory location for receiving logic instructions for executing encrypted program instruction;
- logic circuitry for modifying operation in accordance with logic instructions stored in said memory location;
- and
- logic circuitry configurable in accordance with the received logic instructions.
Dependencies are inferred from the claim text.