Apparatus for performing branch target address calculation based on branch type
AssigneeIP-First, LLC
InventorsG. Glenn Henry, Terry Parks
Life of this patent
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Abstract
A branch target address prediction mechanism is provided. A branch target buffer (BTB) is employed to predict target address only of indirect branch instructions. Return addresses are predicted from a call/return stack and PC-relative branch instructions are predicted by directly calculating the target address using a program counter-relative displacement specified in the instruction. Because the BTB only stores indirect branch instruction target addresses, the likelihood of aliasing collisions in the BTB is greatly reduced, thereby increasing the prediction accuracy of the BTB.
Claims12
An apparatus for predicting target addresses of branch instructions in a pipelined microprocessor, comprising:
- a call/return stack, for storing target addresses, said target addresses related to return instructions;
- an adder, for calculating target addresses, said target addresses related to direct branch instructions;
- a branch target buffer, for storing target addresses, said target addresses related to indirect branch instructions;
- and
- decode logic, coupled to said stack, said adder and said buffer, for decoding an instruction, wherein said decoding comprises determining if said instruction is a return instruction, a direct branch instruction or an indirect branch instruction;
- wherein the predictor selects a target address provided by one of said stack, said adder and said buffer for use by the microprocessor in fetching program instructions in response to determining if a branch instruction is a return, direct branch or indirect branch instruction, wherein said decode logic is configured to select said target address provided by one of said stack, said adder and said buffer based on said determining.
A method for predicting branch target addresses, comprising:
- fetching a branch instruction;
- decoding said branch instruction after said fetching;
- determining if said branch instruction is one of a return instruction, a direct branch instruction and an indirect branch instruction based on said decoding;
- selecting a predicted target address of said branch instruction provided by one of a call/return stack, an adder and a branch target buffer, respectively, in response to said determining;
- and
- fetching a next instruction using said predicted target address in response to said selecting.
Dependencies are inferred from the claim text.