Method and apparatus for multi-thread pipelined instruction decoder

A multithread pipelined instruction decoder comprising:

• an instruction decode pipeline to decode instructions associated with a plurality of instruction threads;
• and
• a shadow pipeline operating in parallel with the instruction decode pipeline, the shadow pipeline including,
• an instruction thread identification pipeline to associate a thread identification at each pipe stage with each instruction being decoded in the instruction decode pipeline, and
• an instruction valid pipeline to associated a valid indicator at each pipe stage with each instruction being decoded in the instruction decode pipeline.

A method of decoding multiple threads of instructions, comprising:

• inputting an instruction of a first thread of instructions, a first instruction thread identification, and a first instruction valid indicator into a pipeline in parallel;
• decoding the instruction of the first thread of instructions;
• maintaining the parallel association between the instruction of the first thread, the first instruction thread identification, and the first instruction valid indicator during the decoding of the instruction of the first thread of instructions;
• inputting an instruction of a second thread of instructions, a second instruction thread identification, and a second instruction valid indicator into a pipeline in parallel;
• decoding the instruction of the second thread of instructions;
• and
• maintaining the parallel association between the instruction of the second thread of instructions, the second instruction thread identification, and the second instruction valid indicator during the decoding of the instruction of the second thread of instructions.

A computer including:

• a memory;
• and
• a microprocessor, the microprocessor including,
• an instruction decoder to decode multiple threads of instructions, the instruction decoder having,
• an instruction decode pipeline to decode each input instruction associated with each thread;
• and
• a shadow pipeline operating in parallel with the instruction decode pipeline, the shadow pipeline including,
• an instruction thread identification pipeline to associate a thread identification with each instruction being decoded in the instruction decode pipeline, and
• an instruction valid pipeline to associated a valid indicator with each instruction being decoded in the instruction decode pipeline.

A microprocessor including:

• an instruction decoder to decode multiple threads of instructions, the instruction decoder having,
• an instruction decode pipeline,
• the instruction decode pipeline to decode each input instruction associated with each thread, and
• the instruction decode pipeline to maintain a thread identification and a valid indicator in parallel with each instruction being decoded in the instruction decode pipeline.