Method and apparatus for speculative microinstruction pairing

A microprocessor for speculatively pairing micro instructions for parallel execution within a single pipeline, the micro instructions paired within the single pipeline when they utilize non-conflicting resources, the microprocessor comprising:

• a translator, for receiving macro instructions, and for generating a pair of micro instructions;
• instruction pair split logic, coupled to said translator, for splitting said pair of micro instructions when they utilize a conflicting resource, wherein said instruction pair split logic comprises:
• a pair indicator, for indicating whether said pair of micro instructions stored in said instruction register may be executed in parallel within the single pipeline;
• and
• an instruction register, coupled to said translator and to said instruction pair split logic, for storing said pair of micro instructions.

A microprocessor for speculatively pairing micro instructions for parallel execution within a single pipeline, the micro instructions paired within the single pipeline when they utilize non-conflicting resources, the microprocessor comprising:

• a translator, for receiving macro instructions, and for generating a pair of micro instructions;
• instruction pair split logic, coupled to said translator, for splitting said pair of micro instructions when they utilize a conflicting resource, wherein said instruction pair split logic comprises:
• instruction redirection logic, coupled to said instruction register, for feeding back one of said pair of micro instructions to said instruction register while said instruction register provides the other of said pair of micro instructions to the single pipeline, thereby effecting a split of said pair of micro instructions;
• and
• an instruction register, coupled to said translator and to said instruction pair split logic, for storing said pair of micro instructions.

A microprocessor for speculatively pairing micro instructions for parallel execution within a single pipeline, the micro instructions paired within the single pipeline when they utilize non-conflicting resources, the microprocessor comprising:

• a translator, for receiving macro instructions, and for generating a pair of micro instructions;
• instruction pair split logic, coupled to said translator, for splitting said pair of micro instructions when they utilize a conflicting resource;
• an instruction register, coupled to said translator and to said instruction pair split logic, for storing said pair of micro instructions;
• and
• an instruction queue, coupled between said translator and said instruction register, for selectively storing said pair of micro instructions until said instruction register becomes available.

A microprocessor for speculatively pairing micro instructions for parallel execution within a single pipeline, the micro instructions paired within the single pipeline when they utilize non-conflicting resources, the microprocessor comprising:

• a translator, for receiving macro instructions, and for generating a pair of micro instructions;
• instruction pair split logic, coupled to said translator, for splitting said pair of micro instructions when they utilize a conflicting resource;
• and
• an execution unit within the single pipeline, configured to receive said pair of micro instructions, and to execute said pair of micro instructions in parallel, wherein said execution unit comprises an MMX execution unit.

An apparatus for selectively unpairing speculatively paired first and second micro instructions for parallel execution within a single pipeline of a microprocessor, the speculative pairing performed by a translator of the microprocessor, the unpairing performed when the micro instructions utilize a conflicting resource, the microprocessor also having an instruction register for storing the first and second micro instructions, the apparatus comprising:

• an unpairing signal generated by the translator for indicating whether the first and second micro instructions utilize the conflicting resource within the single pipeline;
• instruction redirection logic, coupled to the instruction register, for redirecting the second micro instruction to the instruction register;
• and
• control logic, coupled to said instruction redirection logic, configured to control said instruction redirection logic to selectively redirect the second micro instruction to the instruction register in response to said unpairing signal.

A microprocessor for speculatively pairing micro instructions for parallel execution within a single pipeline, comprising:

• a translator for translating macro instructions into paired micro instructions for parallel execution within the single pipeline;
• an instruction register, coupled to said translator, for storing said paired micro instructions;
• at least two resources within the single pipeline of the microprocessor, operatively coupled to said instruction register, for executing micro instructions;
• and
• instruction reorder logic, coupled between said translator and said instruction register, for reordering said paired micro instructions for sequential execution within the single pipeline rather than parallel execution when said paired micro instructions utilize the same one of said at least two resources.

A method for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor, the method comprising:

• pairing first and second micro instructions for parallel execution within the single pipeline;
• determining if said first and second micro instructions utilize a conflicting resource;
• splitting said first and second micro instructions for sequential execution after said pairing if said first and second micro instructions utilize said conflicting resource;
• and
• translating one or more macro instructions into said first and second micro instructions prior to said pairing.

A method for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor, the method comprising:

• pairing first and second micro instructions for parallel execution within the single pipeline;
• determining if said first and second micro instructions utilize a conflicting resource;
• and
• splitting said first and second micro instructions for sequential execution after said pairing if said first and second micro instructions utilize said conflicting resource;
• wherein said splitting said first and second micro instructions comprises:
• programming a status indicator for indicating said first and second micro instructions may not be executed in parallel within the single pipeline.

A method for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor, the method comprising:

• pairing first and second micro instructions for parallel execution within the single pipeline;
• determining if said first and second micro instructions utilize a conflicting resource;
• and
• splitting said first and second micro instructions for sequential execution after said pairing if said first and second micro instructions utilize said conflicting resource;
• wherein said splitting said first and second micro instructions comprises:
• redirecting said second micro instruction for storage in an instruction register if said first and second micro instructions utilize said conflicting resource.

A method for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor, the method comprising:

• pairing first and second micro instructions for parallel execution within the single pipeline;
• determining if said first and second micro instructions utilize a conflicting resource;
• and
• splitting said first and second micro instructions for sequential execution after said pairing if said first and second micro instructions utilize said conflicting resource;
• wherein said pairing is performed during a first clock cycle, the method further comprising:
• executing said first and second micro instructions during a second clock cycle if said first and second micro instructions utilize non-conflicting resources;
• and
• executing said first micro instruction during said second clock cycle and executing said second micro instruction during a third clock cycle if said first and second micro instructions utilize said conflicting resource.

A method for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor, the method comprising:

• pairing first and second micro instructions for parallel execution within the single pipeline;
• determining if said first and second micro instructions utilize a conflicting resource;
• and
• splitting said first and second micro instructions for sequential execution after said pairing if said first and second micro instructions utilize said conflicting resource;
• wherein said pairing comprises:
• storing said first and second micro instructions into an instruction register.

A method for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor, the method comprising:

• pairing first and second micro instructions for parallel execution within the single pipeline;
• determining if said first and second micro instructions utilize a conflicting resource;
• and
• splitting said first and second micro instructions for sequential execution after said pairing if said first and second micro instructions utilize said conflicting resource;
• wherein said splitting said first and second micro instructions comprises:
• programming a status indicator to indicate said first and second micro instructions may not be executed in parallel within the single pipeline.