Microprocessor with primary and secondary issue queue

A microprocessor comprising:

• an instruction cache;
• a dispatch unit configured to receive instructions from the instruction cache;
• and
• an issue unit configured to receive instructions from the dispatch unit, wherein the issue unit is adapted to:
• allocate a dispatched first instruction to a primary issue queue and, upon subsequently determining that the first instruction is ineligible for execution, to move the first instruction to a secondary issue queue;
• and
• allocate a dispatched second instruction to the primary issue queue and upon issuing the second instruction for execution, moving the second instruction to the secondary issue queue wherein the instructions remaining in the primary issue queue are eligible for execution.

A data processing system including at least one processor, memory, input means, and a display, wherein the microprocessor comprises:

• an instruction cache;
• a dispatch unit configured to receive instructions from the instruction cache;
• and
• an issue unit configured to receive instructions from the dispatch unit, wherein the issue unit is adapted to:
• allocate a dispatched first instruction to a primary issue queue and, upon subsequently determining that the first instruction is ineligible for execution, to move the first instruction to a secondary issue queue;
• and
• allocate a dispatched second instruction to the primary issue queue and upon issuing the second instruction for execution, moving the second instruction to the secondary issue queue wherein the instructions remaining in the primary issue queue are eligible for execution.