US 6,608,794 B2Granted

Serial access memory

AssigneeOki Electric Industry Co., Ltd.

InventorShigemi Yoshioka

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Abstract

The present invention provides a serial access memory low in current consumption, which is capable of restraining an increase in chip size even if memory capacity increases. The serial access memory has a first and a second memory arrays a and b each having memory cells electrically connected to their corresponding bit lines BLia, signal lines CLi provided in common between the memory arrays a and b and electrically connected to their corresponding bit lines BLia through first transfer means Ha and Hb, write registers WRm electrically connected to their corresponding signal lines CLi through a second transfer means F, a write bus WD electrically connected to the write registers WRm through a third transfer means D, an input means L electrically connected to the write bus WD, read registers RRm electrically connected to their corresponding signal lines CLi through a fourth transfer means I, a read bus RD electrically connected to the read registers RRm through a fifth transfer means K, and an input means M electrically connected to the read bus RD.

Claims27

Dependent claims

A serial access memory comprising:

a first memory array including a plurality of first memory cells, a plurality of first sense amplifiers and a plurality of pairs of first bit lines connected to the first memory cells and the first sense amplifiers;
a second memory array including a plurality of second memory cells, a plurality of second sense amplifiers and a plurality of pairs of second bit lines connected to the second memory cells and the second sense amplifiers;
a plurality of pairs of column lines each of which is selectively connected to a corresponding one of the pairs of first bit lines in said first memory array or a corresponding one of the pairs of second bit lines in said second memory array according to a select information;
a plurality of first word lines each of which is connected to corresponding ones of the first memory cells;
a plurality of second word lines each of which is connected to corresponding ones of the second memory cells;
a plurality of write registers each of which is connected to a corresponding one of the pairs of column lines;
a write address accessing circuit connected to said write registers for selecting one of said write registers;
a plurality of read registers each of which is connected to a corresponding one of the pairs of column lines;
a read address accessing circuit connected to said read registers for selecting one of said read registers;
an input circuit connected to said write registers;
and
an output circuit connected to said read registers,
wherein each of the first word lines is not crossed by the pairs of second bit lines, and each of the second word lines is not crossed by the pairs of first bit lines.

10 more elements

A serial access memory comprising:

a first memory array including a plurality of first memory cells, a plurality of first sense amplifiers and a plurality of first and second pairs of bit lines connected to the first memory cells and the first sense amplifiers;
a second memory array including a plurality of second memory cells, a plurality of second sense amplifiers and a plurality of third and fourth pairs of bit lines connected to the second memory cells and the second sense amplifiers;
a plurality of pairs of first column lines each of which is selectively connected to one of the first pairs of bit lines or one of the third pairs of the bit lines;
a plurality of pairs of second column lines each of which is selectively connected to one of the second pairs of bit lines or one of the fourth pairs of the bit lines;
a plurality of write registers;
a plurality of first transfer circuits each of which is connected between one of said first column lines and one of said write registers, said first transfer circuits connecting the first column lines to said write registers in response to a first control signal;
a plurality of second transfer circuits each of which is connected between one of said second column lines and one of said write registers, said second transfer circuits connecting the second column lines to said write registers in response to a second control signal;
a write address accessing circuit connected to said write registers for selecting one of said write registers;
a plurality of read registers;
a plurality of third transfer circuits each of which is connected between one of said first column lines and one of said read registers, said third transfer circuits connecting the first column lines to said read registers in response to a third control signal;
a plurality of fourth transfer circuits each of which is connected between one of said second, column lines and one of said read registers, said fourth transfer circuits connecting the second column lines to said read registers in response to a fourth control signal;
a read address accessing circuit connected to said read registers for selecting one of said read registers;
an input circuit connected to said write registers;
and
an output circuit connected to said read registers.

12 more elements

A serial access memory comprising:

a first memory array including a plurality of first memory cells, a plurality of first sense amplifiers and a plurality of first and second pairs of bit lines connected to the first memory cells and the first sense amplifiers;
a second memory array including a plurality of second memory cells, a plurality of second sense amplifiers and a plurality of third and fourth pairs of bit lines connected to the second memory cells and the second sense amplifiers;
a plurality of pairs of column lines each of which is selectively connected to one of said first pairs of bit lines, one of said second pairs of bit lines, one of said third pairs of bit lines or one of said fourth pairs of bit lines;
a plurality of first transfer circuits each of which is connected between one of said column lines and one of said first pairs of bit lines, said first transfer circuits connecting the column lines to said first pairs of bit lines in response to a first control signal;
a plurality of second transfer circuits each of which is connected between one of said column lines and one of said second pairs of bit lines, said second transfer circuits connecting the column lines to said second pairs of bit lines in response to a second control signal;
a plurality of third transfer circuits each of which is connected between one of said column lines and one of said third pairs of bit lines, said third transfer circuits connecting the column lines to said third pairs of bit lines in response to a third control signal;
a plurality of fourth transfer circuits each of which is connected between one of said column lines and one of said fourth pairs of bit lines, said fourth transfer circuits connecting the column lines to said fourth pairs of bit lines in response to a fourth control signal;
a plurality of write registers;
a write address accessing circuit connected to said write registers for selecting one of said write registers;
a plurality of read registers;
a read address accessing circuit connected to said read registers for selecting one of said read registers;
an input circuit connected to said write registers;
and
an output circuit connected to said read registers.

11 more elements

A serial access memory comprising:

a first memory array including a plurality of first memory cells, a plurality of first sense amplifiers and a plurality of pairs of first bit lines connected to the first memory cells and the first sense amplifiers;
a second memory array including a plurality of second memory cells, a plurality of second sense amplifiers and a plurality of pairs of second bit lines connected to the second memory cells and the second sense amplifiers;
a plurality of pairs of column lines each of which is selectively connected to a corresponding one of the pairs of first bit lines in said first memory array or a corresponding one of the pairs of the second bit lines in said second memory array according to a select information;
a first decoding section consisting of first word lines each of which is connected to corresponding ones of the first memory cells, said first decoding section having a first decoder for selectively activating one of the first word lines according to a decoding result by the first decoder;
a second decoding section consisting of second word lines each of which is connected to corresponding ones of the second memory cells, said second decoding section having a second decoder for selectively activating one of the second word lines according to a decoding result by the second decoder;
a plurality of write registers each of which is connected to a corresponding one of the pairs of column lines;
a write address accessing circuit connected to said write registers for selecting one of said write registers;
a plurality of read registers each of which is connected to a corresponding one of the pairs of column lines;
a read address accessing circuit connected to said read registers for selecting one of said read registers;
an input circuit connected to said write registers;
and
an output circuit connected to said read registers.

9 more elements

Dependencies are inferred from the claim text.