Apparatus and method for a memory storage cell leakage cancellation scheme

A method, comprising:

• a) pre-charging a first bit line through a first transistor and pre-charging a second bit line through a second transistor;
• b) drawing a first leakage supply current from said first transistor to supply one or more leakage currents drawn from said first bit line by one or more storage cells coupled to said first bit line and drawing a second leakage supply current from said second transistor to supply one or more leakage currents drawn from said second bit line by one or more storage cells coupled to said second bit line, said first and second bit lines not being equalized so as to allow said first and second bit lines to possess different voltages;
• c) equalizing said first and second bit lines to force said voltages on said first and second bit lines to approach the same voltage, while, said first and second leakage supply currents are maintained;
• and
• d) continuing to maintain said first and second leakage supply currents during a read of a storage cell that is coupled to said first bit line and said second bit line.

An apparatus, comprising:

• a memory coupled to a processor, said memory further comprising:
• a) a plurality of storage cells coupled between a first bit line and a second bit line;
• b) a first transistor that:
• 1) provides, prior to said bit lines being equalized, a first supply of current in order to supply one or more leakage currents drawn from said first bit line by any of said plurality of storage cells
• 2) maintains, while said bit lines are being said equalized, said first supply of current in order to continue to supply said one or more leakage currents drawn from said first bit line and
• 3) maintains, after said bit lines are no longer being said equalized so as to allow any of said plurality of storage cells to be read, said first supply of current in order to continue to supply said one ore more leakage currents drawn from said first bit line;
• and
• c) a second transistor that:
• 1) provides, prior to said bit lines being said equalized, a second supply of current in order to supply one or more leakage currents drawn from said second bit line by any of said plurality of storage cells
• 2) maintains, while said bit lines are being said equalized, said second supply of current in order to continue to supply said one or more leakage currents drawn from said second bit line and
• 3) maintains, after said bit lines are no longer being said equalized so as to allow any of said plurality of storage cells to be read, said second supply of current in order to continue to supply said one ore more leakage currents drawn from said first bit line.