Twisted bit-line compensation

A memory, comprising:

• an array of rows and columns of memory cells;
• a plurality of sense amplifiers, each one having a true terminal and a compliment terminal;
• a plurality of pairs of bit lines, each one of the pairs of lines being coupled to a corresponding one of the plurality of sense amplifiers, one of bit lines in the pair being connected to the memory cells in a first one of the columns of such cells and and the other one of the bits lines in the pair being connected to the memory cells in the second one of the columns of such memory cells, one of the lines in each pair of bit lines being coupled to the true terminal of the coupled one of the sense amplifiers and the other one of the lines of such pair of lines being coupled to the terminal of the coupled one of the sense amplifiers;
• a plurality of word lines each one being connected to a corresponding one of the rows of memory cells;
• an address logic section fed by column address signals fed to the bit lines and row address signals coupled to the word lines for producing invert/non-invert signals in accordance with the fed row and column address signals;
• a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.