US 6,608,782 B2 · Booster circuit capable of achieving a stable pump operation for nonvolatile semiconductor memory device

Abstract

A p-MOS transistor 38 is connected to an intermediate node 5. A level shifter 39 supplies an output signal hresetb to a gate of the p-MOS transistor 38 based on a signal Reset. Then, in an initial state until a pump operation is started, the signal Reset is set at “H” to turn on the p-MOS transistor 38. Thus, a positive charge of the intermediate node 5 is discharged via the p-MOS transistor 38 and a negative charge is discharged via an N-well of the p-MOS transistor 38 so that the potential of the intermediate node 5 becomes about 0.7 V. Therefore, even when the pump operation is started and the p-MOS transistor 38 is turned off, the maximum voltage applied to each of the capacitors C4a, C4b is 4 V, and exceeding of the withstand voltage of a capacitor insulating film can be prevented.

Claims6

Dependent claims

A booster circuit of a nonvolatile semiconductor memory device having a plurality of capacitors, generating a voltage different from a power source voltage during a write operation and an erase operation and supplying the voltage to the nonvolatile semiconductor memory device, wherein

among those capacitors, a capacitor to which a high electric field exceeding a withstand voltage of an insulating film constituting each capacitor is applied is constituted by two or more partial capacitors connected to each other in series;
the booster circuit, comprising:
a transistor element connected between the partial capacitors;
and
control means, which turns on the transistor element when the nonvolatile semiconductor memory device is in an inoperative state and turns off the transistor element when the device is in an operative state.

2 more elements

Dependencies are inferred from the claim text.

Booster circuit capable of achieving a stable pump operation for nonvolatile semiconductor memory device

Life of this patent

Booster circuit capable of achieving a stable pump operation for nonvolatile semiconductor memory device

Life of this patent

Abstract

Claims6