High performance semiconductor memory devices
OwnerJeng-Jye Shauinventor
Life of this patent
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Abstract
High performance memory devices have been realized by applying an Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit-line-write mechanism allows us to reduce the number of bit lines by 50% for static memory devices. The resulting memory device can be as fast as registers files while its area is smaller than prior art high-density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuits in future IC manufacture technologies.
Claims22
A semiconductor memory array comprising a plurality of memory cells wherein each of said memory cells are further connected to a bit-line and a word-line for reading and writing a data signal from said memory cell, said memory array further comprising:
- a power supply for providing a high and a low memory cell voltages represented by CVss and CVdd respectively;
- and
- a read/write impedance adjustment means connected between said power supply and said memory cells for providing adjusting an impedance of said read/write impedance adjustment means for providing different voltages of said CVss and CVdd in a read and a write cycle.
A five-transistor static random access memory (SRAM) cell connected to a power supply for providing a high and a low memory cell voltages represented by CVss and CVdd respectively comprising:
- four transistors connected as back-to-back inverters to form a static latch for storing a data bit therein;
- a fifth transistor interconnecting said static latch to a wordline and a single bit-line to carry out a single port read and write functions using said single bit-line;
- and
- a read/write impedance adjustment means connected between said power supply and said memory cells for providing adjusting an impedance of said read/write impedance adjustment means for providing different voltages of said CVss and CVdd in a read and a write cycle.
A dual-port six-transistor static random access memory (SRAM) cell connected to a power supply for providing a high and a low memory cell voltages represented by CVss and CVdd respectively comprising:
- four transistors connected as back-to-back inverters to form a static latch for storing a data bit therein;
- a fifth transistor interconnecting said static latch to a first wordline and a first bit-line to carry out a first port read and write functions using said first bit-line;
- a sixth transistor interconnecting said static latch to a second wordline and a second bit-line to carry out a second port read and write functions using said second bit-line;
- and
- a read/write impedance adjustment means connected between said power supply and said memory cells for providing adjusting an impedance of said read/write impedance adjustment means for providing different voltages of said CVss and CVdd in a read and a write cycle.
A four-port eight-transistor static random access memory (SRAM) cell connected to a power supply for providing a high and a low memory cell voltages represented by CVss and CVdd respectively comprising:
- four transistors connected as back-to-back inverters to form a static latch for storing a data bit therein;
- a fifth transistor interconnecting said static latch to a first wordline and a first bit-line to carry out a first port read and write functions using said first bit-line;
- a sixth transistor interconnecting said static latch to a second wordline and a second bit-line to carry out a second port read and write functions using said second bit-line;
- a seventh transistor interconnecting said static latch to a third wordline and a third bit-line to carry out a third port read and write functions using said third bit-line;
- a eighth transistor interconnecting said static latch to a fourth wordline and a fourth bit-line to carry out a fourth port read and write functions using said fourth bit-line;
- and
- a read/write impedance adjustment means connected between said power supply and said memory cells for providing adjusting an impedance of said read/write impedance adjustment means for providing different voltages of said CVss and CVdd in a read and a write cycle.
A three-transistor-two-resistor (3T2R) static random access memory (SRAM) cell connected to a power supply for providing a high and a low memory cell voltages represented by CVss and CVdd respectively comprising:
- two transistors connected with two resistors as back-to-back inverters to form a static latch for storing a data bit therein;
- and
- a third transistor interconnecting said static latch to a wordline and a single bit-line to carry out a single port read and write functions using said single bit-line;
- and
- a read/write impedance adjustment means connected between said power supply and said memory cells for providing adjusting an impedance of said read/write impedance adjustment means for providing different voltages of said CVss and CVdd in a read and a write cycle.
A five-transistor static random access memory (SRAM) cell connected to a power supply for providing a high and a low memory cell voltages represented by CVss and CVdd respectively comprising:
- four NMOS transistors connected as back-to-back inverters to form a static latch for storing a data bit therein;
- and
- a fifth NMOS transistor interconnecting said static latch to a wordline and a single bit-line to carry out a single port read and write functions using said single bit-line;
- and
- a read/write impedance adjustment means connected between said power supply and said memory cells for providing adjusting an impedance of said read/write impedance adjustment means for providing different voltages of said CVss and CVdd in a read and a write cycle.
A dual-port four-transistor two-resistor (4T2R) static random access memory (SRAM) cell connected to a power supply for providing a high and a low memory cell voltages represented by CVss and CVdd respectively comprising:
- two transistors connected to two resistors as back-to-back inverters to form a static latch for storing a data bit therein;
- a third transistor interconnecting said static latch to a first wordline and a first bit-line to carry out a first port read and write functions using said first bit-line;
- and
- a fourth transistor interconnecting said static latch to a second wordline and a second bit-line to carry out a second port read and write functions using said second bit-line;
- and
- a read/write impedance adjustment means connected between said power supply and said memory cells for providing adjusting an impedance of said read/write impedance adjustment means for providing different voltages of said CVss and CVdd in a read and a write cycle.
A semiconductor memory array comprising a plurality of memory cells wherein each of said memory cells are further connected to a bit-line and a word-line for reading and writing a data signal from said memory cell, said memory array further comprising:
- a power supply for providing a high and a low memory cell voltages represented by CVss and CVdd respectively;
- a read/write impedance adjustment means connected between said power supply and said memory cells for adjusting an impedance of said read/write impedance adjustment means for providing different voltages of said CVss and CVdd in a read and a write cycle;
- each of said bit-lines is connected to a signal sensing circuit operable at a logic-signal sensing level whereby memory signal sensing is not disturbed by logic-circuit noises.
An integrated circuit (IC) comprising:
- a memory array comprising a plurality of memory cells wherein each of said memory cells are further connected to a bit-line and a word-line for reading and writing a data signal from said memory cell;
- a power supply for providing a high and a low memory cell voltages to each of said memory cells represented by CVss and CVdd respectively and said power supply is provided for a supplying voltages of different CVss and CVdd during a read and a write cycle;
- each of said bit-lines is connected to a signal sensing circuit operable at a logic-signal sensing level whereby memory signal sensing is not disturbed by logic-circuit noises;
- a logic circuit array disposed immediately next to said memory array.
Dependencies are inferred from the claim text.