Method and apparatus for low power memory
AssigneeIntel Corporation
InventorsRichard J. Burgess, Jr., Lawrence T. Clark, Kimberley E. Wagner, Mark A. Schaecher
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Abstract
Embodiments are disclosed that include a low power memory and/or a low power data path. One particular embodiment, for example, includes a technique to reduce power consumption. In one particular embodiment, for example, a grouping of bits, such as a 32-bit word, for example, is stored in inverted form if more than half of the bits have a bit value of logic “1” rather than logic “0.” Likewise, in this embodiment, if more than half of the bits have a bit value of logic “0” rather than logic “1,” then the grouping of bits is not stored in inverted form.
Claims26
An integrated circuit comprising:
- a memory adapted to store a grouping of bits in inverted form if more than half of the bits of the grouping have a first bit value.
A data path for manipulating bits comprising:
- a memory;
- and
- bit manipulation circuitry coupled with said memory;
- said memory and bit manipulation circuitry being adapted to process groupings of bits of a predetermined size;
- said memory and bit manipulation circuitry being further adapted to process a grouping of bits in inverted form if more than half of the bits of the grouping are a first bit value.
A method of storing a grouping of binary digital signals comprising:
- storing the binary digital signals in inverted form if more than half of the bits have a first bit value.
Dependencies are inferred from the claim text.