Delay locked loop, synchronizing method for the same and semiconductor device equipped with the same

A semiconductor device, comprising:

• a delay locked loop that comprises:
• a delay circuit that receives an external clock external to the delay locked loop and outputs an internal clock delayed by a delay time from the external clock;
• an output circuit that outputs data synchronized with the internal clock;
• a phase comparison circuit that compares the phase of output data of the output circuit with the phase of the external clock;
• and
• a delay time changing means for changing the delay time according to a phase comparison result of said phase comparison circuit;
• wherein said delay locked loop conducts a delay locked operation to generate the internal clock synchronized with the external clock only when a command signal is supplied to the delay locked loop, and said delay time changing means retains a current delay time when the command signal is not supplied.

A semiconductor device, comprising:

• a delay circuit that receives an external clock external to the delay locked loop and outputs an internal clock delayed by a delay time from the external clock;
• a plurality of output circuits that output a plurality of data synchronized with the internal clock ICK;
• a phase comparison circuit that compares the phase of a dummy pattern that is supplied to and output from a particular one of said plurality of output circuits, said dummy pattern being formed so that “H” level and “L” level are repeated at a given cycle and a given ratio, with the phase of the external clock;
• and
• a delay time changing means for changing the delay time according to a phase comparison result of said phase comparison circuit;
• wherein a delay locked operation to generate the internal clock synchronized with the external clock is conducted only when a command signal is supplied, and when the command signal is not supplied, said delay time changing means retains a current delay time and said output circuit which receives the dummy pattern outputs the data synchronized with the internal clock ICK.

A method for adjusting a phase of an internal clock signal using a delay locked loop, the method comprising:

• receiving an external clock signal;
• producing an internal clock signal delayed by a delay time from the external clock signal;
• outputting data from an output circuit in synch with the internal clock signal;
• comparing the phase of the data output from the output circuit with the phase of the external clock signal to produce a difference signal;
• and
• altering the delay time based on the difference signal;
• wherein
• the comparing is performed only when a command signal is supplied;
• and
• when the command signal is not supplied, a current delay time is used.