Top gate TFT structure having light shielding layer and method to fabricate the same

A method of fabricating a TFT liquid crystal display device, comprising the steps of:

• depositing a light shielding layer on a substrate;
• depositing an interlayer insulating layer on said light shielding layer;
• forming source/drain electrodes on said interlayer insulating layer;
• depositing a semiconductor layer on said interlayer insulating layer with overlaying said source/drain electrodes;
• depositing a gate insulating layer on said semiconductor layer;
• depositing a gate metal layer on said gate insulating layer;
• forming a resist pattern for use in forming a gate electrode on said gate metal layer;
• patterning said gate metal layer, said gate insulating layer and said semiconductor layer using said resist pattern as a mask;
• patterning said interlayer insualting layer and said light shielding layer using said source/drain electrodes as a mask;
• removing said resist pattern;
• forming an orientation film thus completing a TFT array side substrate;
• forming a color filter side substrate;
• disposing said TFT array side substrate and said color filter side substrate so as to face each other;
• and
• injecting a liquid crystal layer between said TFT array side substrate and said color filter side substrate.

A TFT liquid crystal display device comprising:

• a pair of substrates provided so as to face each other;
• a liquid crystal layer located between said substrates;
• a non-metallic light shielding layer provided on a surface of one of said substrate, the surface facing said liquid crystal layer;
• an interlayer insulating layer provided on said non-metallic light insulating layer;
• source/drain electrodes provided on said interlayer insulating layer;
• a semiconductor layer provided on said interlayer insulating layer, the semiconductor layer partially covering said source/drain electrodes;
• a gate insulating layer formed on said semiconductor layer;
• and
• a gate electrode provided on said gate insulating layer;
• wherein a periphery of said semiconductor layer is inside of a periphery of said non-metallic light shielding layer and does not cross the periphery of said light shielding layer, and wherein said non-metallic light shielding layer, said interlayer insulating layer and source/drain electrodes each have periphery edges that are in alignment with each other.

A top gate TFT array comprising:

• a substrate;
• a non-metallic light shielding layer formed on said substrate;
• an interlayer insulating layer formed on said non-metallic light shielding layer;
• source/drain electrodes formed on said interlayer insulating layer;
• a semiconductor layer formed on said interlayer insulating layer and overlaying partially said source/drain electrodes;
• a gate insulating layer formed on said semiconductor layer;
• and
• a gate electrode formed on said gate insulating layer,
• wherein a periphery of said semiconductor layer is inside of a periphery of said non-metallic light shielding layer and does not cross the periphery of said light shielding layer, and wherein said non-metallic light shielding layer, said interlayer insulating layer and source/drain electrodes each have periphery edges that are in alignment with each other.