Differential analog-to-digital converter

A method for converting a plurality of input signals being indicative of a signal to be converted to a digital output, comprising:

• setting a plurality of codes each being indicative of a corresponding reference level;
• and, for each one of said codes,
• converting said one code to a first analog signal, and summing said first analog signal with a first of said input signals to provide a first summed signal;
• complementing said one code to provide a complemented code, converting said complemented code to a second analog signal, and summing said second analog signal with a second of said input signals to provide a second summed signal corresponding to said first summed signal;
• comparing said corresponding first and second summed signals to provide a comparison signal;
• and,
• setting at least a portion of said digital output according to said comparison signal, wherein at least one same decoder is used for converting said code to said first analog signal and converting said complemented code to said second analog signal.

An analog to digital converter, comprising:

• a comparator including a plurality of inputs and at least one output;
• a register including an input and an output, said register input being coupled to said comparator output, and said register supplying a code at said register output corresponding to said comparator output;
• circuitry for complementing said code to provide a complemented code;
• at least one digital-to-analog converter coupled between said register output and at least one of said comparator inputs so as to receive said code and complemented code and provide analog signals corresponding to said code and complemented code;
• and
• at least one summing circuit at least partially responsive to said analog signal corresponding to said code or complemented code and to one of a plurality of differential input wherein said summing circuit subtracts said analog signal from said one of said differential inputs.

An analog to digital converter, comprising:

• a comparator including a plurality of inputs and at least one output;
• a register including an input and an output, said register input being coupled to said comparator output, and said register supplying a code at said register output corresponding to said comparator output;
• circuitry for complementing said code to provide a complemented code;
• at least one digital-to-analog converter coupled between said register output and at least one of said comparator inputs so as to receive said code and complemented code and provide analog signals corresponding to said code and complemented code;
• and
• a plurality of adders, wherein at least one of said adders is at least partially responsive to an output of one of said digital-to-analog converters corresponding to said code or complemented code.