Enhanced ZDB feedback methodology utilizing binary weighted techniques
AssigneeCypress Semiconductor Corporation
InventorsDavid Green, Daigo Katagiri
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to a first control signal. The first control signal may be configured to minimize a difference in delay between the plurality of output clock signals.
Claims20
An apparatus comprising:
- a first circuit configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal;
- and
- a second circuit configured to select one of said plurality of output clock signals as said feedback signal in response to a first control signal, wherein said first control signal is configured to minimize a difference in delay between said plurality of output clock signals.
An apparatus for minimizing a difference in delay between a plurality of output clock signals comprising:
- means for generating said output clock signals in response to a reference clock signal and a feedback signal;
- and
- means for selecting one of said output clock signals as said feedback signal in response to a control signal.
A method for minimizing a difference in delay between a plurality of output clock signals comprising the steps of:
- (A) generating said output clock signals in response to a reference clock signal and a feedback signal;
- and
- (B) selecting one of said output clock signals as said feedback signal in response to a control signal.
Dependencies are inferred from the claim text.