Methods and systems for limiting supply bounce
AssigneeBroadcom Corporation
InventorJanardhanan S. Ajit
Life of this patent
Estimating the term…
Abstract
Methods and systems for limiting power supply and ground bounce enables control of the output current drive dependent on the changes in supply (VDD and GND) levels. This is made possible by making the gate drive of the output driver PMOS and NMOS dependent on the VDD and GND swings. When the VDD or GND increases above normal operating levels, the gate drive of the output driver PMOS is reduced and when the GND or VDD reduces below normal operating levels, the gate drive of the output driver NMOS is reduced. This leads to reduced current flow between the supplies and the pad thereby reducing the VDD and GND bounce problem.
Claims34
An output circuit, comprising:
- an input terminal;
- an output terminal;
- a plurality of buffer circuits including inputs coupled to said input terminal;
- a plurality of output drivers, each output driver including;
- a control terminal coupled to an output of a corresponding one of said buffer circuits,
- a second terminal coupled to said supply output through a supply line,
- a third terminal coupled to said output terminal, and
- wherein said plurality of output drivers selectively couple said supply output to said output terminal under control of said plurality of buffer circuits;
- and
- a plurality of sensing and control circuits, each sensing and control circuit coupled to said supply output and to a corresponding one of at least a portion of said plurality of output drivers, each sensing and control circuit including;
- sensing circuitry that senses voltage changes with respect to time at said supply output, and
- control circuitry that increasingly disables said at least a portion of said plurality of output drivers with increasing voltage changes with respect to time at said supply output.
An apparatus for limiting supply bounce in an output circuit, wherein said output circuit includes an input terminal for receiving a waveform, an output terminal for outputting said waveform, a plurality of output drivers coupled to a supply output through supply lines, and buffer circuitry that control said plurality of output drivers to selectively couple said supply output to said output terminal in response to said input waveform, wherein switching circuits coupled to said supply lines interact with inductances of said supply lines to cause current changes in said supply lines that lead to voltage changes in said supply output, and wherein said voltage changes cause unwanted current flow between said supply output and said output terminal, said apparatus comprising:
- a plurality of sensing and control circuits coupled to said supply output and to a corresponding one of at least a portion of said plurality of output drivers, each said sensing and control circuit including sensing circuitry that senses voltage changes with respect to time at said supply output and control circuitry that increasingly disables said at least a portion of said plurality of output drivers with increasing voltage changes with respect to time at said supply output, thereby reducing said unwanted current in said supply lines to thereby compensate for said voltage changes in said supply output.
A method for limiting supply bounce in an output circuit, wherein said output circuit includes an input terminal for receiving a waveform, an output terminal for outputting said waveform, and a plurality of output drivers coupled to one or more supply outputs through supply lines, wherein said output drivers selectively couple said one or more supply outputs to said output terminal in response to said input waveform to substantially reproduce said input waveform at said output waveform, and wherein switching circuits coupled to said supply lines interact with inductances of said supply lines, thereby causing current changes in said supply lines, which lead to undesirable voltage changes in said one or more supply outputs, comprising;
- (1) receiving said waveform;
- (2) selectively coupling said one or more supply outputs to said output terminal in response to said received waveform, using said plurality of output drivers;
- (3) sensing for voltage changes with respect to time at a first one of said supply outputs;
- (4) disabling at least a portion of a said plurality of output drivers when voltage changes with respect to time are sensed at said first one of said supply outputs, thereby reducing current in said supply lines to thereby compensate for said voltage changes.
A method for limiting source bounce, comprising:
- (1) providing rising-edge and falling-edge output current drive to an output pad in response to a waveform received at an input pad, using a PMOS output driver and an NMOS output driver, respectively, wherein said PMOS output driver and said NMOS output driver are powered by first and second supplies, respectively;
- (2) sensing for transients at said first and second supplies;
- (3) disabling at least a portion of said PMOS output driver when a transient is sensed at said first supply;
- and
- (4) disabling at least a portion of said NMOS output driver when a transient is sensed at said second supply.
An apparatus for limiting source bounce, comprising the steps of:
- means for providing rising-edge and falling-edge output current drive to an output pad in response to a waveform received at an input pad, using a PMOS output driver and an NMOS output driver, respectively, wherein said PMOS output driver and said NMOS output driver are powered by first and second supplies, respectively;
- means for sensing for transients at said first and second supplies;
- means for disabling at least a portion of said PMOS output driver when a transient is sensed at said first supply;
- and
- means for disabling at least a portion of said NMOS output driver when a transient is sensed at said second supply.
An output circuit, comprising:
- an input terminal;
- an output terminal;
- a plurality of buffer circuits including inputs coupled to said input terminal;
- a plurality of output drivers, each output driver including;
- a PMOS and an NMOS coupled between a supply VDD and GND,
- a control terminal coupled to an output of a corresponding one of said buffer circuits,
- a second terminal coupled to said supply VDD,
- a third terminal coupled to said GND, and
- a fourth terminal coupled to said output terminal,
- wherein said plurality of output drivers selectively couple said supply VDD or GND to said output terminal under control of said plurality of buffer circuits;
- and
- a plurality of sensing and control circuits, each sensing and control circuit coupled to said supply VDD or GND and to a corresponding one of at least a portion of said plurality of output drivers, each sensing and control circuit including;
- sensing circuitry that senses voltage changes with respect to time at said supply VDD or GND, and
- control circuitry that increasingly disables said at least a portion of said plurality of output drivers with increasing voltage changes with respect to time at said supply output.
An apparatus for limiting supply bounce in an output circuit, wherein said output circuit includes an input terminal for receiving a waveform, an output terminal for outputting said waveform, a plurality of output drivers coupled to a supply output through supply lines, and buffer circuitry that control said plurality of output drivers to selectively couple said supply output to said output terminal in response to said input waveform, wherein switching circuits coupled to said supply lines interact with inductances of said supply lines to cause current changes in said supply lines that lead to voltage changes in said supply output, and wherein said voltage changes cause unwanted current flow between said supply output and said output terminal, said apparatus comprising:
- a plurality of sensing and control circuits coupled to said supply output and to a corresponding one of at least a portion of said plurality of output drivers, each said sensing and control circuit including sensing circuitry that senses voltage changes with respect to time at said supply output and control circuitry that increasingly disables said at least a portion of said plurality of output drivers with increasing or decreasing voltage changes with respect to time at said supply output, thereby reducing said unwanted current in said supply lines to thereby compensate for said voltage changes in said supply output.
A method for limiting supply bounce in an output circuit, wherein said output circuit includes an input terminal for receiving a waveform, an output terminal for outputting said waveform, and a plurality of output drivers coupled to one or more supply outputs through supply lines, wherein said output drivers selectively couple said one or more supply outputs to said output terminal in response to said input waveform to substantially reproduce said input waveform at said output waveform, and wherein switching circuits coupled to said supply lines interact with inductances of said supply lines, thereby causing current changes in said supply lines, which lead to undesirable voltage changes in said one or more supply outputs, comprising;
- (1) receiving said waveform;
- (2) selectively coupling said one or more supply outputs to said output terminal in response to said received waveform, using said plurality of output drivers;
- (3) sensing for voltage changes with respect to time at a first one of said supply outputs;
- (4) disabling at least a portion of a said plurality of output drivers when voltage changes with respect to time are sensed at said first one of said supply outputs, thereby reducing current in said supply lines to thereby compensate for said voltage changes.
A method for limiting source bounce, comprising:
- (1) providing rising-edge and falling-edge output current drive to an output pad in response to a waveform received at an input pad, using a PMOS output driver and an NMOS output driver, respectively, wherein said PMOS output driver and said NMOS output driver are powered by first and second supplies, respectively;
- (2) sensing for transients at said first and second supplies;
- (3) disabling at least a portion of said PMOS output driver when a transient is sensed at said second supply;
- and
- (4) disabling at least a portion of said NMOS output driver when a transient is sensed at said first supply.
An apparatus for limiting source bounce, comprising the steps of:
- means for providing rising-edge and falling-edge output current drive to an output pad in response to a waveform received at an input pad, using a PMOS output driver and an NMOS output driver, respectively, wherein said PMOS output driver and said NMOS output driver are powered by first and second supplies, respectively;
- means for sensing for transients at said first and second supplies;
- means for disabling at least a portion of said PMOS output driver when a transient is sensed at said second supply;
- and
- means for disabling at least a portion of said NMOS output driver when a transient is sensed at said first supply.
Dependencies are inferred from the claim text.