Clock signal generator circuit and semiconductor integrated circuit with the same circuit

A clock signal generator circuit comprising:

• an off-chip driver which outputs high-level data on the basis of a first control signal, and outputs low-level data on the basis of a second control signal, wherein a signal delay time from when the first control signal is inputted until the high-level data is outputted is different from a signal delay time from when the second control signal is inputted until the low-level data is outputted;
• a first control signal generator circuit which generates said first control signal inputted to said off-chip driver and, in response, said off-chip driver outputting high-level data on the basis of said first control signal;
• and
• a second control signal generator circuit which generates said second control signal inputted to said off-chip driver and, in response, said off-chip driver outputting low-level data on the basis of said second control signal;
• and
• wherein said first control signal generator circuit includes
• a first clock control circuit which receives a first clock signal and outputs a second clock signal synchronizing with the first-clock signal and, when said off-chip driver outputs high-level data, advanced in phase with respect to the first clock signal by the signal delay time from when said first control signal is inputted to said off-chip driver until the data is outputted,
• a second clock control circuit which receives a third clock signal and generates a fourth clock signal, said fourth clock signal being synchronous with the third clock signal, having the same frequency as the second clock signal, being different in phase from the second clock signal and advanced in phase with respect to the third clock signal by a signal delay time when the off-chip driver outputs high-level data, said signal delay time being a period that starts when the first control signal is input to the off-chip driver and ends when the data is output from the off-chip driver, and
• a first OR circuit which receives the second clock signal and the fourth clock signal and outputs a fifth clock signal for controlling the data output operation of said off-chip driver outputting high-level data, and
• said second control signal generator circuit includes
• a third clock control circuit which receives a sixth clock signal and outputs a seventh clock signal synchronizing with the sixth clock signal and, when said off-chip driver outputs low-level data, advanced in phase with respect to the sixth clock signal by the signal delay time from when said second control signal is inputted to said off-chip driver until the data is outputted,
• a fourth clock control circuit which receives an eighth clock signal and generates a ninth clock signal, said ninth clock signal being synchronous with the eighth clock signal, having the same frequency as the seventh clock signal, being different in phase from the seventh clock signal and advanced in phase with respect to the eighth clock signal by a signal delay time when the off-chip driver outputs low-level data, said signal delay time being a period that starts when the second control signal is input to the off-chip driver and ends when the data is output from the off-chip driver, and
• a second OR circuit which receives the seventh clock signal and the ninth clock signal and outputs a tenth clock signal for controlling the data output operation of said off-chip driver outputting low level data.

A clock signal generator circuit comprising:

• a first clock control circuit which receives a first clock signal and outputs a second clock signal;
• a control circuit which cuts off at least a first pulse of the second clock signals outputted from the first clock control circuit and thereafter sequentially outputs a group of pulse signals outputted from the first clock control circuit;
• and
• a second clock control circuit which receives the group of pulse signals outputted from said control circuit and outputs a third clock signal.

A clock signal generator comprising:

• a first clock control circuit which includes a first delay monitor circuit which receives and outputs a clock signal, and a first synchronous adjusting delay circuit which has a first forward delay array and a first backward delay array, said first synchronous adjusting delay circuit receiving a first clock signal and the clock signal outputted from the first delay monitor circuit, causing the first forward delay array to delay, for a specific delay time, the clock signal outputted from the first delay monitor circuit after the input of the first clock signal in a first cycle, said first synchronous adjusting delay circuit causing the first backward delay array to delay the first clock signal in a second cycle following the first cycle for a time equivalent to the delay time in the clock signal delayed by the first forward delay array or n/m of the delay time (where n and m are positive integers), after the first clock signal in the second cycle has arrived, and which outputs a second clock signal;
• a control circuit which is inserted between an input node of the first clock signal and the first synchronous adjusting delay circuit of said first clock control circuit and which cuts off at least a first pulse of the first clock signal and thereafter sequentially outputs the first clock signal supplied to the input node;
• and
• a second clock control circuit which receives the second clock signal from the first clock control circuit and outputs a third clock signal.

A clock control circuit comprising:

• an input buffer which receives a clock signal;
• a delay monitor circuit to which the output of the input buffer is inputted and which has a specific amount of signal delay;
• a first delay array which is composed of a plurality of first delay circuits cascade-connected in a multistage manner and causes the cascade-connected first delay circuits to delay the output of the delay monitor circuit sequentially;
• a sense circuit to which the output of the input buffer is inputted and which senses the first delay circuits through which the output of the delay monitor circuit has passed in the first delay array during one period from when the delay monitor circuit outputs the clock signal in a first cycle until the clock signal in a second clock following the first cycle is outputted;
• a second delay array which is composed of a plurality of second delay circuits cascade-connected in a multistage manner and which causes the second delay circuit at the stage corresponding to the result of the sensing at the sense circuit to select the clock signal in the second cycle outputted from the delay monitor circuit, and sequentially delays the selected clock signal through the second delay circuits at the stages following the stage corresponding to the result;
• and
• an output buffer to which the output of the second delay array is inputted, wherein said delay monitor circuit has the amount of signal delay equivalent to the sum of the amount of signal delay in said input buffer and that in said output buffer and the second delay circuits, at least the last stage in said second delay array delays only the output of the second delay circuit at the preceding stage without receiving said clock signal outputted from said delay monitor circuit.