Full rail drive enhancement to differential SEU hardening circuit

A hardening circuit for an integrated circuit having a data state reinforcing feedback path with a data node Q and a data complement node QN comprising:

• a first hardening transistor coupled between a rail and the data node Q, wherein the first hardening transistor is arranged to provide additional drive to the data node Q;
• a second hardening transistor coupled between the rail and the data complement node QN, wherein the second hardening transistor is arranged to provide additional drive to the data complement node QN;
• a first gate control circuit coupled between a clock input and a gate of the first hardening transistor, wherein the first gate control circuit includes first and second transistor paths each having a control input, wherein the control input of the first transistor path is coupled to the data node Q, and wherein the control input of the second transistor path is coupled to the data complement node QN;
• a second gate control circuit coupled between the clock input and a gate of the second hardening transistor, wherein the second gate control circuit includes third and fourth transistor paths each having a control input, wherein the control input of the third transistor path is coupled to the data complement node QN, and wherein the control input of the fourth transistor path is coupled to the data node Q;
• wherein the first and second gate control circuits are arranged to provide full rail drive to internal nodes of the hardening circuit.

A hardening system comprising:

• a positive-level-sensitive D latch having a data input, a clock input, and a data state reinforcing feedback path having a data node Q and a data complement node QN, wherein the positive-level-sensitive D latch is coupled between rails VDD and VSS;
• a first p-channel hardening transistor coupled between the rail VDD and the data node Q, wherein the first p-channel hardening transistor is arranged to provide drive to the data node Q in addition to drive provided by the positive-level-sensitive D latch;
• a second p-channel hardening transistor coupled between the rail VDD and the data complement node QN, wherein the second p-channel hardening transistor is arranged to provide drive to the data complement node QN in addition to drive provided by the positive-level-sensitive D latch;
• a first gate control circuit coupled between the clock input and a gate of the first p-channel hardening transistor, wherein the first gate control circuit includes a first n-channel transistor path and a first p-channel transistor path each having a control input, wherein the control input of the first n-channel transistor path is coupled to the data node Q, and wherein the control input of the first p-channel transistor path is coupled to the data complement node QN;
• a second gate control circuit coupled between the clock input and a gate of the second p-channel hardening transistor, wherein the second gate control circuit includes a second n-channel transistor path and a second p-channel transistor path each having a control input, wherein the control input of the second p-channel transistor path is coupled to the data node Q, and wherein the control input of the second n-channel transistor path is coupled to the data complement node QN;
• wherein the first and second gate control circuits are arranged to provide full rail drive to the internal nodes of the hardening system.

A hardening system comprising:

• a negative-level-sensitive D latch having a data input, a clock input, and a data state reinforcing feedback path having a data node Q and a data complement node QN, wherein the negative-level-sensitive D latch is coupled between rails VDD and VSS;
• a first n-channel hardening transistor coupled between the rail VDD and the data node Q, wherein the first n-channel hardening transistor is arranged to provide drive to the data node Q in addition to drive provided by the negative-level-sensitive D latch;
• a second n-channel hardening transistor coupled between the rail VDD and the data complement node QN, wherein the second n-channel hardening transistor is arranged to provide drive to the data complement node QN in addition to drive provided by the negative-level-sensitive D latch;
• a first gate control circuit coupled between the clock input and a gate of the first n-channel hardening transistor, wherein the first gate control circuit includes a first n-channel transistor path and a first p-channel transistor path each having a control input, wherein the control input of the first n-channel transistor path is coupled to the data complement node QN, and wherein the control input of the first p-channel transistor path is coupled to the data node Q;
• a second gate control circuit coupled between the clock input and a gate of the second n-channel hardening transistor, wherein the second gate control circuit includes a second n-channel transistor path and a second p-channel transistor path each having a control input, wherein the control input of the second p-channel transistor path is coupled to the data complement node QN, and wherein the control input of the second n-channel transistor path is coupled to the data node Q;
• wherein the first and second gate control circuits are arranged to provide full rail drive to the internal nodes of the hardening system.