Charge-pump phase-locked loop circuit with charge calibration

A charge-pump phase-locked loop, comprising:

• a first charge pump circuit for providing a first current to cause an output clock signal's phase to track a reference clock signal's phase;
• a first transistor arranged in cascade connection with the first charge pump circuit for fine tuning the first current based on a calibrate voltage signal to eliminate a first net charge delivered from the first current;
• a calibration circuit comprising:
• a second phase detector, receiving the reference clock signal, for simultaneously generating a second pump-up pulse and a second pump-down pulse at a rate of the reference clock signal;
• a second charge pump, responsive to the second pump-up and the second pump-down pulses, for providing a second current to simulate the first current in a condition in which the phase of the output clock signal is locked onto the phase of the reference clock signal;
• a second transistor arranged in cascade connection with the second charge pump for fine tuning the second current based on the calibrate voltage signal to eliminate a second net charge delivered from the second current;
• and
• a charge sensing circuit for generating the calibrate voltage signal in accordance with the first net charge and the second net charge, and for providing the calibrate voltage signal as feedback to the first and the second transistors;
• wherein the first charge pump with the first transistor and the second charge pump with the second transistor, under control of the calibrate voltage signal, respectively regulate the first net charge and the second net charge to become exactly zero thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.

A charge-pump phase-locked loop with charge calibration, comprising:

• a first charge pump for providing a first current to cause an output clock signal's phase to track a reference clock signal's phase;
• and
• a calibration circuit comprising:
• a second phase detector, receiving the reference clock signal, for simultaneously generating a second pump-up pulse and a second pump-down pulse at a rate of the reference clock signal;
• a second charge pump coupled to the second phase detector, for providing a second current in response to the second pump-up and the second pump-down pulses, wherein the second current is used to simulate the first current in a condition in which the phase of the output clock signal is locked onto the phase of the reference clock signal;
• and
• an operational amplifier having a first input terminal coupled to an output terminal of the first charge pump, a second input terminal coupled to an output terminal of the second charge pump, and an output terminal connected to a control node of the first charge pump and a control node of the second charge pump respectively, for providing a calibrate voltage signal as feedback to the first charge pump and the second charge pump;
• wherein the first and the second charge pumps, under control of the calibrate voltage signal, respectively regulate a first net charge on the first input terminal of the operational amplifier and a second net charge on the second input terminal of the operational amplifier to become exactly zero thereby maintaining the phase of the output clock signal locked onto the phase of the reference clock signal.