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US 6,608,500 B1Granted
I/O architecture/cell design for programmable logic device
AssigneeCypress Semiconductor Corporation
InventorsTimothy M. Lacey, David L. Johnson
Life of this patent
Estimating the term…
Abstract
An apparatus comprising an input/output circuit and a programmable logic device. The input/output circuit may be configured to (i) connect to an end of a bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate said one or more control signals.
Claims20
An apparatus comprising:
- an input/output circuit configured to (i) connect to an end of a bus and (ii) operate in one or more modes in response to one or more first control signals, said input/output circuit comprising one or more input/output cells comprising a first register configured to generate an output enable signal;
- and
- a programmable logic device configured to generate said one or more first control signals.
An apparatus comprising:
- means for communicating input/output signals configured to (i) connect to an end of a bus and (ii) operate in one or more modes in response to one or more control signals, said input/output means comprising a register configured to generate an output enable signal;
- and
- means for programmably generating said one or more control signals.
A method of laying out a programmable logic device comprising the steps of:
- (A) placing a routing channel parallel to an axis of said programmable logic device, said routing channel having a first and a second end;
- and
- (B) connecting a first input/output circuit, configured to operate in one or more modes in response to one or more control signals generated by said programmable logic device, to said first end of said routing channel, wherein said first input/output circuit comprises one or more input/output cells comprising a register configured to generate an output enable signal.
Dependencies are inferred from the claim text.