Semiconductor device with stress relieving layer comprising circuit board and electronic instrument
AssigneeSeiko Epson Corporation
InventorNobuaki Hashimoto
Life of this patent
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Abstract
A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided on the semiconductor chip, wiring (154) formed from the electrodes (158) to over the resin layer (152), and solder balls (157) formed on the wiring (154) over the resin layer (152); the resin layer (152) is formed so as to have a depression (152a) in the surface, and the wiring (154) is formed so as to pass over the depression (152a).
Claims14
A semiconductor device comprising:
- a semiconductor chip having electrodes;
- a first stress relieving layer provided on the semiconductor chip;
- a first conducting portion formed from the electrodes over the first stress relieving layer, the first conducting portion having a bent portion;
- and
- external electrodes formed on the first conducting portion positioned above the first stress relieving layer,
- wherein at least a part of the bent portion is positioned between one of the electrodes and one of the external electrodes, avoiding an area above the one of the electrodes and avoiding an area below the one of the external electrodes.
Dependencies are inferred from the claim text.