Delamination-preventing substrate and semiconductor package with the same

A semiconductor package with a delamination-preventing substrate, the semiconductor package comprising:

• a substrate having a first surface and a second surface opposed to the first surface, the first surface being formed with a chip attach area that is covered by a metal layer thereon, wherein a solder mask layer is applied over the metal layer and the first surface of the substrate, and formed with a plurality of first openings corresponding in position to the metal layer, allowing a portion of the metal layer to be exposed, and the exposed portion of the metal layer is formed with a plurality of second openings respectively within the first openings, so as to partly expose the first surface of the substrate to the second openings;
• at least a chip having a first surface and a second surface opposed to the first surface, wherein the second surface of the chip is attached to the chip attach area on the first surface of the substrate;
• an adhesive layer for attaching the second surface of the chip to the chip attach area of the substrate, wherein the adhesive layer fills into the first and second openings to be in contact with the exposed part of the first surface of the substrate;
• a plurality of bonding wires bonded to the first surface of the chip and to the first surface, outside the chip attach area, of the substrate, so as to electrical connect the chip to the substrate by means of the bonding wires;
• an encapsulant formed on the first surface of the substrate, for encapsulating the chip and the bonding wires;
• and
• a plurality of solder bumps implanted on the second surface of the substrate, for electrically connecting the chip to an external device.