Enhanced chip scale package for flip chips

A chip scale package for connecting a flip chip die having signal and ground connections to a primary circuit board, said chip scale package comprising:

• a substrate comprising a top side with a mounting area for receiving the flip chip die and a bottom side for connecting said substrate to the primary circuit board;
• a first set of signal and ground pads on said top side of said substrate to electrically connect with the corresponding signal and ground connections on the flip chip die;
• a second set of signal and ground pads on said bottom side of said substrate to electrically connect the flip chip die with the primary circuit board;
• a plurality of signal and ground conductive paths extending from said top side to said bottom side of said substrate to electrically connect respective ones of said first set of signal and ground pads with respective ones of said second set of signal and ground pads,
• a ground plane on said bottom side of said substrate within a central area substantially beneath said mounting area of the flip chip die;
• a plurality of grounded thermal vias extending upward through said substrate from said ground plane;
• a plurality of conductive traces to connect selected ones of said ground conductive paths to respective ones of said grounded thermal vias to electrically connect said selected ones of said ground conductive paths to said ground plane;
• and
• a plurality of thermal solder balls coupled to said ground plane to provide electrically and thermally conductive paths from said ground plane to the primary circuit board.

A chip scale package to couple a flip chip die having a set of signal and ground connections with a primary circuit board, said chip scale package comprising:

• a substrate comprising top and bottom sides, said top side of said substrate having a mounting area for receiving the flip chip die;
• a first set of pads on said top side of said substrate arranged in an alternating pattern of signal and ground pads to electrically connect with the set of signal and ground pads on the flip chip die;
• a second set of pads on said bottom side of said substrate corresponding to said first set of pads, said second set of pads arranged in an alternating pattern of signal and ground pads;
• a plurality of conductive paths extending through said substrate and interconnecting corresponding ones of said first and second sets of pads in an alternating signal and ground pattern;
• a ground plane on said bottom side of said substrate in an area of said bottom side substantially opposite said mounting area on said top side;
• a plurality of thermal vias extending upward from said ground plane into said mounting area on said top side of said substrate to provide low thermal impedance paths between the flip chip die and said ground plane;
• and
• a plurality of thermal solder balls coupled to said ground plane to extend the low thermal impedance paths to the primary circuit board;
• and conductive traces coupling selected ones of said conductive paths to respective ones of said thermal vias to establish electrically conductive paths from the flip chip die to said ground plane.

A chip scale package for a flip chip die having a set of signal and ground connections, said chip scale package comprising comprising:

• a substrate comprising top and bottom sides, said top side of said substrate comprising a mounting area to receive the die;
• a first array of alternating ground and signal pads disposed on said top side of said substrate to electrically connect with corresponding ones in the set of signal and ground connections on the die;
• a second array of alternating ground and signal pads disposed on said bottom side of said substrate corresponding to said first array, said pads in said second array adapted to carry solder balls for attaching said substrate to a primary circuit board;
• a central ground plane disposed on said bottom side of said substrate and positioned substantially opposite said mounting area on said top side of said substrate;
• a first plurality of vias for electrically connecting said pads on said top side with said pads on said bottom side, respective ones of said first and second arrays of pads coupled to said vias by conductive traces on said respective top and bottom sides of said substrate;
• a second plurality of vias positioned within said mounting area on said top side of substrate, and extending from said top side into said central ground plane on said bottom side to provide thermal conduction paths between the die and said central ground plane, selected ones of said conductive traces extending to connect said second plurality of vias to electrical ground;
• and
• a plurality of thermal solder balls coupled to said central ground plan to provide thermal and electrical connections between said central ground plane and the primary circuit board.