Determination of thermal resistance for field effect transistor formed in SOI technology
AssigneeAdvanced Micro Devices, Inc.
InventorsWei Long, Michael Lee
Life of this patent
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Abstract
In a system for determining thermal resistance of a field effect transistor, a p-n junction is formed with one of drain and source regions of the transistor for determining a current versus temperature characteristic of the p-n junction. A respective temperature of the transistor is determined for each of a plurality of power dissipation levels through the transistor from the current versus temperature characteristic of the p-n junction. The thermal resistance is a rate of change of the temperature with respect to a rate of change of the power dissipation level for the field effect transistor.
Claims14
A system for determining thermal resistance of a field effect transistor, comprising:
- a p-n junction formed with one of drain and source regions of the transistor for determining a current versus temperature characteristic of the p-n junction;
- and
- means for determining a respective temperature for each of a plurality of power dissipation levels for the transistor from the current versus temperature characteristic)
- wherein the thermal resistance of the transistor is a rate of change of the temperature with respect to a rate of change of the power dissipation level.
A system for determining thermal resistance of a field effect transistor formed with a semiconductor film on a buried insulating material in SOI (semiconductor on insulator) technology, the field effect transistor having a drain region and a source region, the system comprising:
- a p-n junction formed with at least one of the drain region or the source region;
- a p-n junction voltage source for biasing the p-n junction at a bias voltage;
- a wafer heating chuck for heating the p-n junction to a plurality of temperatures;
- a p-n junction current meter for measuring a current conducted through the p-n junction at each of the plurality of temperatures of the p-n junction to generate a current versus temperature characteristic for the p-n junction;
- a drain to source voltage source and a gate to source voltage source for biasing the field effect transistor to dissipate a power dissipation level;
- and
- a drain to source current meter for measuring a drain to source current of the field effect transistor,
- wherein the p-n junction current meter measures a respective current flowing through the p-n junction as the field effect transistor is dissipating each of a plurality of power dissipation levels and with the p-n junction being biased by the p-n junction voltage source at the bias voltage;
- wherein a respective temperature of the p-n junction is determined from the measured respective current and the current versus temperature characteristic for each of the plurality of power dissipation levels,
- and wherein the thermal resistance is determined to be a rate of change of the temperature of the p-n junction with respect to a rate of change of the power dissipation level.
Dependencies are inferred from the claim text.