Nonvolatile semiconductor memory device and semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• an SOI substrate in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order;
• a plurality of memory cell transistors formed in a memory cell array portion of said SOI substrate;
• and
• a plurality of low-voltage transistors formed in a low-voltage portion of said SOI substrate, being driven by a voltage lower than a driving voltage of said plurality of memory cell transistors,
• wherein said plurality of memory cell transistors and said plurality of low-voltage transistors each have a source region and a drain region which are formed away from each other in said semiconductor layer,
• said source region or a depletion layer in a pn junction between said source region and said semiconductor layer in each of said plurality of memory cell transistors does not reach said insulating layer,
• both said source region and said drain region or both depletion layers in pn junctions between said source region and said semiconductor layer and between said drain region and said semiconductor layer in each of said plurality of low-voltage transistors reach said insulating layer,
• a film thickness of said semiconductor layer in said low-voltage portion is the same as that of said semiconductor layer in said memory cell array portion, and
• wherein a depth from a main surface of said semiconductor layer to bottom surfaces of said source region and said drain region of each of said plurality of low-voltage transistors is deeper than that from said main surface of said semiconductor layer to a bottom surface of said source region of each of said plurality of memory cell transistors.