Image sensor with an enhanced near infra-red spectral response and method of making
AssigneeISE TEX, Inc
InventorJaroslav Hynecek
Life of this patent
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Abstract
Image sensors with an enhanced QE and MTF in the NIR spectral region are fabricated on the standard substrates. This is achieved by replacing the p+ type doped layer, typically present under the thick field oxide in the inactive regions of the sensor, with an n+ type doped layer. The n+ type layer, which is biased at the Vdd potential, surrounds the entire image sensor array as a guard ring and is separated from the CCD or CMOS array pixels by a suitable potential barrier. The potential barrier prevents collected charge from escaping into the n+ layer regions. Additional embodiments include output diode and MOS transistor designs that use field plates for creating potential barriers that separate these devices from the n+ type doped field regions.
Claims20
A CCD Sensor Array, comprising:
- a sensor array having n-type CCD channels fabricated on a p-type substrate;
- an n+ type peripheral region completely surrounding and contiguous to said sensor array, said n+ peripheral region being completely surrounded and separated from another p+ type peripheral region that is contiguous with the p-type substrate;
- wherein the separation between the n+ type and p+ type peripheral regions is at least partially depleted of mobile carriers by a suitable bias applied between the said p+ type and n+ type peripheral regions.
A modified CMOS circuit consisting of at least one p-type transistor enclosed by an n+ type peripheral region and placed in an n-type well that is contiguous with the n+ type peripheral region, said CMOS circuit furthermore including at least one n-type transistor that is completely surrounded by a field plate, the field plate being further surrounded by the n+ type peripheral region and the substrate under the field plate in the vicinity of the n-type transistor, and at a semiconductor-dielectric interface depleted of mobile carriers.
A CCD Sensor Array, comprising:
- a sensor array having p-type CCD channels fabricated on a n-type substrate;
- an p+ type peripheral region completely surrounding and contiguous to said sensor array, said p+ peripheral region being completely surrounded and separated from another n+ type peripheral region that is contiguous with the n-type substrate;
- wherein the separation between the p+ type and n+ type peripheral regions is at least partially depleted of mobile carriers by a suitable bias applied between the said n+ type and p+ type peripheral regions.
A modified CMOS circuit consisting of at least one n-type transistor enclosed by an p+ type peripheral region and placed in an p-type well that is contiguous with the p+ type peripheral region, said CMOS circuit furthermore including at least one p-type transistor that is completely surrounded by a field plate, the field plate being further surrounded by the p+ type peripheral region and the substrate under the field plate in the vicinity of the p-type transistor, and at a semiconductor-dielectric interface depleted of mobile carriers.
Dependencies are inferred from the claim text.