Lateral double diffused MOS transistor
AssigneeSanyo Electric Co., Ltd.
InventorsShuichi Kikuchi, Eiji Nishibe
Life of this patent
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Abstract
To reduce ON-state resistance with desired withstand voltage secured, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjacent to the gate electrode, an N-type source region and a channel region respectively formed in the LP layer, an N-type drain region formed in a position apart from the LP layer and an LN layer (a drift region) formed so that the LN layer surrounds the drain region is characterized in that a P-type layer ranging to the LP layer is formed under the gate electrode.
Claims8
A semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, a first conductive type of body region formed so that the body region is adjacent to the gate electrode, a second conductive type of source region and a channel region respectively formed in the first conductive type of body region, a second conductive type of drain region formed in a position apart from the first conductive type of body region and a second conductive type of drift region formed so that the drift region surrounds the drain region, wherein:
- a first conductive type of impurity layer ranging to the first conductive type of body region is formed under the gate electrode.
Dependencies are inferred from the claim text.