High-speed vision sensor having a parallel processing system
AssigneeHamamatsu Photonics K.K.
InventorsHaruyoshi Toyoda, Masatoshi Ishikawa
Life of this patent
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Abstract
A high-speed vision sensor has: an analog-to-digital converter array 13 including analog-to-digital converters 210 corresponding to respective lines of photodetectors 120 of a photodetector array 11, and a parallel processing system 14 including processing elements 400 and shift registers 410. The processing elements 400 are provided in one to one correspondence with the photodetectors 120. The shift registers 410 are provided in one to one correspondence with the photodetectors 120. Because the processing elements 400 carry out the image processing between neighboring pixels by parallel processing at high speed, independently from the operation in the shift registers 410, the processing and shifting can be performed efficiently.
Claims11
A high-speed vision sensor, comprising;
- at least one photodetector array, each having a plurality of photodetectors which are arranged two-dimensionally in a plurality of rows and in a plurality of columns;
- an analog-to-digital converter array having a plurality of analog-to-digital converters which are arranged one-dimensionally such that each analog-to-digital converter corresponds to one row in the at least one photodetector array, each analog-to-digital converter converting, into digital signals, analog signals which are successively outputted from the photodetectors in the corresponding row;
- a parallel processing system, including a parallel processing element array and a shift register array, the parallel processing element array having a plurality of processing elements which are arranged two-dimensionally in a plurality of rows and in a plurality of columns and in one-to-one correspondence with the plurality of photodetectors in the at least one photodetector array, each processing element performing a predetermined calculation on digital signals transferred from the analog-to-digital converter array, the shift register array having a plurality of shift registers which are disposed in one-to-one correspondence with the plurality of analog-to-digital converters and in one-to-one correspondence with the plurality of rows of processing elements, each shift register successively transferring digital signals, which are received from the corresponding analog-to-digital converter and which are equivalent to signals outputted from the photodetectors in a corresponding photodetector row, to predetermined processing elements in the corresponding row;
- and
- a control circuit controlling the photodetector array and the analog-to-digital converter array to output digital signals for a single frame and controlling the shift register array to transfer the digital signals of the single frame to the parallel processing element array, and thereafter controlling the photodetector array and the analog-to-digital converter array to output digital signals for the next frame and controlling the shift register array to transfer the digital signals of the next frame to the parallel processing element array, while simultaneously controlling the parallel processing element array to perform the predetermined calculation onto the single frame.
Dependencies are inferred from the claim text.