Method of manufacturing semiconductor device

A manufacturing method of a semiconductor device, in which a dynamic random access memory and a logical circuit are arranged, comprising:

• a step of depositing a side wall spacer forming film and a silicide protection film after forming a gate electrode on a gate oxide film formed on a silicon substrate;
• a step of forming a first resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a first conductive channel MOS transistor after depositing the silicide protection film;
• a step of removing a portion of the silicide protection film exposed from the opening of the first resist pattern after the formation of the first resist pattern to form a first opening in the silicide protection film;
• a step of forming a first side wall spacer on a side wall of a gate electrode of the first conductive channel MOS transistor after the formation of the first opening and forming the source/drain diffusion layer of the first conductive channel MOS transistor;
• a step of removing the first resist pattern and forming a first silicide layer on the source/drain diffusion layer of the first conductive channel MOS transistor exposed from the first opening of the silicide protection film;
• a step of forming a second resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a second conductive channel MOS transistor after the formation of the first silicide layer;
• a step of removing a portion of the silicide protection film exposed from the opening of the second resist pattern after the formation of the second resist pattern to form a second opening in the silicide protection film;
• a step of forming a second side wall spacer on a side wall of a gate electrode of the second conductive channel MOS transistor after the formation of the second opening and forming the source/drain diffusion layer of the second conductive channel MOS transistor;
• and
• a step of removing the second resist pattern, forming a second silicide layer on the source/drain diffusion layer of the second conductive channel MOS transistor exposed from the second opening of the silicide protection film and forming a third silicide layer on the first silicide layer exposed from the first opening of the silicide protection film.

A manufacturing method of a semiconductor device, in which a dynamic random access memory and a logical circuit are arranged, comprising:

• a step of depositing a side wall spacer forming film after forming a gate electrode on a gate oxide film formed on a silicon substrate;
• a step of forming a first resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a first conductive channel MOS transistor after depositing the side wall spacer forming film;
• a step of forming a first side wall spacer on a side wall of a gate electrode of the first conductive channel MOS transistor after the formation of the first resist pattern and forming the source/drain diffusion layer of the first conductive channel MOS transistor;
• a step of removing the first resist pattern and forming a second resist pattern having an opening at a prescribed position corresponding to a source/drain diffusion layer of a second conductive channel MOS transistor;
• a step of forming a second side wall spacer on a side wall of a gate electrode of the second conductive channel MOS transistor after the formation of the second resist pattern and forming the source/drain diffusion layer of the second conductive channel MOS transistor;
• a step of removing the second resist pattern and depositing a silicide protection film;
• a step of forming a third resist pattern having a plurality openings so as to place one opening on the source/drain diffusion layer of the first conductive channel MOS transistor through the silicide protection film and to place another opening on the source/drain diffusion layer of the second conductive channel MOS transistor through the silicide protection film;
• a step of removing portions of the silicide protection film exposed from the openings of the third resist pattern after the formation of the third resist pattern to form both a first opening placing on the source/drain diffusion layer of the first conductive channel MOS transistor and a second opening placing on the source/drain diffusion layer of the second conductive channel MOS transistor in the silicide protection film;
• a step of forming a first silicide layer on the source/drain diffusion layer of the first conductive channel MOS transistor exposed from the first opening of the silicide protection film and forming a second silicide layer on the source/drain diffusion layer of the second conductive channel MOS transistor exposed from the second opening of the silicide protection film;
• a step of removing the second silicide layer;
• and
• a step of forming a third silicide layer in a space, from which the second silicide layer is removed and which is exposed from the second opening of the silicide protection film, and forming a fourth silicide layer on the first silicide layer exposed from the first opening of the silicide protection film.