MIS transistors with a metal gate and high-k dielectric and method of forming
AssigneeInteruniversitair Microelektronic Centrum (IMEC)
InventorsKirklen Henson, Rita Rooyackers, Serge Vanhaelemeersch, Goncal Badenes
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Abstract
A replacement gate process is disclosed comprising the steps of forming a dummy gate stack on a substrate, depositing a PMD layer on the substrate and polishing this PMD layer to expose the top surface of the dummy gate stack. The dummy gate stack can be removed selective to the spacers and the PMD layer. SiC is used as spacer or CMP stop layer to improve the uniformity of the PMD CMP step. SiC can also be used as etch stop layer during the etching of the contact holes or during the formation of a T-gate.
Claims30
A method of forming a MIS transistor comprising the steps of
- forming an active area region on a semiconductor substrate;
- forming a temporary gate stack within said active area region, the temporary gate stack comprising a top layer of a first material;
- forming spacers aligned with and adjacent to said temporary gate stack, said spacers comprising a second material, wherein said second material being selectively removable with respect to said first material;
- depositing a first dielectric layer on top of said semiconductor substrate;
- forming a Pre-Metal Dielectric (PMD) layer on top of said first dielectric layer;
- selectively removing said PMD layer at a removal rate that is higher than removal rate of said top layer, until said top layer of said temporary gate stack is exposed;
- removing said temporary gate stack thereby creating a cavity in said first dielectric layer, and
- forming at least in said cavity a stack of a high-k dielectric and a stack of at least one conductive layer.
A method of forming a metal insulator silicon (MIS) transistor, the method comprising:
- forming a gate stack comprising a layer of a first material on top of a semiconductor substrate;
- forming a plurality of sidewall spacers that are substantially aligned with and adjacent to the gate stack, the plurality of spacers comprising a second material;
- forming a Pre-Metal Dielectric (PMD) layer on top of said first material;
- selectively removing said PMD layer at a removal rate that is higher than removal rate of said first material;
- removing the gate stack thereby creating a cavity;
- and
- forming in at least a portion of the cavity a high-k dielectric layer and a stack of at least one conductive layer.
Dependencies are inferred from the claim text.