Computer-aided timing adjusting method and apparatus

A computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, said semiconductor integrated circuit including sequential circuits, each of said sequential circuits having first and second flip-flops and a combinational circuit connected between an output of said first flip-flop and the input of said second flip-flop, said first and second flip-flops operating in synchronization with a clock, said sequential circuits having first and second sequential circuits whose combinational circuits have a common part, said method comprising:

• preparing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in said combinational circuits;
• when said timing error information in which first and second sequential circuits each are timing error paths, then judging whether or not the types of the timing errors of said timing error paths are the same;
• and
• if the types are the same, then, in order to lower the degree of the both timing errors, replacing a cell in said common part with a cell, in said logic information, with the same function and a different driving capability, or inserting a cell in said logic information into said common part without changing the function of said common part.

A computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, said semiconductor integrated circuit including sequential circuits, each of said sequential circuits having first and second flip-flops and a combinational circuit connected between an output of said first flip-flop and the input of said second flip-flop, said first and second flip-flops operating in synchronization with a clock, said sequential circuits having first and second sequential circuits whose combinational circuits have a common part, said method comprising:

• preparing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in said combinational circuits;
• when said timing error information in which first and second sequential circuits each are timing error paths, then judging whether or not the types of the timing errors of said timing error paths are the same;
• and
• if the types are the same, then, in order to lower the degree of the both timing errors, replacing a cell in said combinational circuit of said first sequential circuit and not in said common part with a cell, with the same function and a different driving capability, or inserting a cell in said logic information into said common part without changing the function of said common part.

A computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, said semiconductor integrated circuit including sequential circuits, each of said sequential circuits having first and second flip-flops and a combinational circuit connected between an output of said first flip-flop and the input of said second flip-flop, said first and second flip-flops operating in synchronization with a clock, said sequential circuits having first and second sequential circuits whose combinational circuits have a common part, said method comprising:

• preparing a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in said combinational circuits;
• when said timing error information in which first and second sequential circuits each are timing error paths, then judging whether or not the types of the timing errors of said timing error paths are the same;
• and
• if the types are different, then, counting the number of set-up error paths and the number of hold error paths for each cell in said first sequential circuit;
• selecting a cell based on the counted number in accordance with a rule of a priority order;
• and
• in order to lower the degree of the timing errors, replacing the selected cell with a cell, in said logic information, with the same function and a different driving capability, or inserting a cell, in said logic information, before or after the selected cell so as not to change the function as before insertion.

A storage medium stored with a program for executing a computer-aided timing adjusting method for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, said semiconductor integrated circuit including sequential circuits, each of said sequential circuits having first and second flip-flops and a combinational circuit connected between an output of said first flip-flop and the input of said second flip-flop, said first and second flip-flops operating in synchronization with a clock, said method comprising:

• preparing a timing error information including the types of timing errors and timing error paths, a delay information relating to signal propagation delay, and a logic information including function and driving capability of each cell in said combinational circuits;
• when said timing error information in which sequential circuit is a set-up error path, then selecting a cell which is estimated with referring to said delay information to be the greatest cause for the set-up error arising;
• searching a cell whose function is the same as the selected cell and driving capability is larger than said selected cell;
• and
• replacing said selected cell with the searched cell.

A computer-aided timing adjusting apparatus for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, said semiconductor integrated circuit including sequential circuits, each of said sequential circuits having first and second flip-flops and a combinational circuit connected between an output of said first flip-flop and the input of said second flip-flop, said first and second flip-flops operating in synchronization with a clock, said apparatus comprising:

• a storage device that stores a timing error information including the types of timing errors and timing error paths, a delay information relating to signal propagation delay, and a logic information including function and driving capability of each cell in said combinational circuits;
• and
• a computer that executes operations of
• when said timing error information in which sequential circuit is a set-up error path, then selecting a cell which is estimated with referring to said delay information to be the greatest cause for the set-up error arising,
• searching a cell whose function is the same as the selected cell and driving capability is larger than said selected cell, and
• replacing said selected cell with the searched cell.

A computer-aided timing adjusting apparatus for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, said semiconductor integrated circuit including sequential circuits, each of said sequential circuits having first and second flip-flops and a combinational circuit connected between an output of said first flip-flop and the input of said second flip-flop, said first and second flip-flops operating in synchronization with a clock, said sequential circuits having first and second sequential circuits whose combinational circuits have a common part, said apparatus comprising:

• a storage device that stores a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability, of each cell in said combinational circuits;
• and
• a computer that executes operations of
• when said timing error information in which first and second sequential circuits each are timing error paths, then judging whether or not the types of the timing errors of said timing error paths are the same, and
• if the types are the same, then, in order to lower the degree of the both timing errors, replacing a cell in said common part with a cell, in said logic information, with the same function and a different driving capability, or inserting a cell in said logic information into said common part without changing the function of said common part.

A computer-aided timing adjusting apparatus for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, said semiconductor integrated circuit including sequential circuits, each of said sequential circuits having first and second flip-flops and a combinational circuit connected between an output of said first flip-flop and the input of said second flip-flop, said first and second flip-flops operating in synchronization with a clock, said sequential circuits having first and second sequential circuits whose combinational circuits have a common part, said apparatus comprising:

• a storage device that stores a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in said combinational circuits;
• and
• a computer that executes operations of
• when said timing error information in which first and second sequential circuits each are timing error paths, then judging whether or not the types of the timing errors of said timing error paths are the same, and
• if the types are the same, then, in order to lower the degree of the both timing errors, replacing a cell in said combinational circuit of said first sequential circuit and not in said common part with a cell, with the same function and a different driving capability, or inserting a cell in said logic information into said common part without changing the function of said common part.

A computer-aided timing adjusting apparatus for adjusting a timing in a semiconductor integrated circuit whose layout and wiring have been designed, said semiconductor integrated circuit including sequential circuits, each of said sequential circuits having first and second flip-flops and a combinational circuit connected between an output of said first flip-flop and the input of said second flip-flop, said first and second flip-flops operating in synchronization with a clock, said sequential circuits having first and second sequential circuits whose combinational circuits have a common part, said apparatus comprising:

• a storage device that stores a timing error information including the types of timing errors and timing error paths, and a logic information including function and driving capability of each cell in said combinational circuits;
• and
• a computer that executes operations of
• when said timing error information in which first and second sequential circuits each are timing error paths, then judging whether or not the types of the timing errors of said timing error paths are the same, and
• if the types are different, then, counting the number of set-up error paths and the number of hold error paths for each cell in said first sequential circuit,
• selecting a cell based on the counted number in accordance with a rule of a priority order, and
• in order to lower the degree of the timing errors, replacing the selected cell with a cell, in said logic information, with the same function and a different driving capability, or inserting a cell, in said logic information, before or after the selected cell so as not to change the function as before insertion.