Method and system for using error and filter layers in each DRC rule

Abstract

A method automatically specifies a unique number of an error layer for each DRC rule in a runset. Therefore, all errors related to a given DRC rule are reported by a layout verification tool in the uniquely specified error layer. Furthermore, the method also automatically specifies a unique number of a filter layer that has the same extent as a quality assurance (QA) cell for testing the DRC rule. The filter layer is logically operated (e.g. ANDed) with the error layer to uniquely identify a failure related to the DRC rule (i.e. errors from all other QA cells are filtered out). The QA cells are generated automatically by use of a library of templates. During regression testing, the first time a DRC runset is run against a test design or QA cell library the results are manually verified and stored as “expected” results. Thereafter when the runset changes or a new version of the verification tool becomes available the test data may be used to identify any differences in the new results, by automatic comparison with the expected results. Specifically, the regression testing method graphically compares the new test results with the expected results and highlights the differences. A utility automatically compares a first set and a second set of shapes in the two sets of results, and can be used for comparison of any two drawings (not necessarily integrated circuit layouts).

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