Simulation method and compiler for hardware/software programming
OwnerDavid J. Greavesinventor
Life of this patent
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Abstract
A method for converting a hardware description language describing an integrated circuit or software operating thereon to an alternative programming language, such as ANSI C, C++, Java, or other object-oriented programming language, is described. The method provides for the single compilation operations as well as the ability to link multiple compilations to simulate large hardware description language designs. The method of the present invention improves the run time efficiency of the compiled code in a more user-friendly format.
Claims16
A method for simulating the operation of an integrated circuit, comprising:
- accessing a section of hardware description language which describes the operations of the integrated circuit, said section of hardware description language comprising at least one module;
- determining which at least one module of said section of hardware description language to include in a simulation;
- flattening each of said at least one modules determined to be included in said simulation into a single module;
- compiling said single module to an unordered list of assignments;
- sorting said unordered list of assignments into sorted sequential groups and sorted combinatorial groups of assignments;
- and
- compiling said sorted sequential groups and said sorted combinatorial groups into a alternative programming language.
A method for converting a hardware description language to an alternative programming language, comprising:
- reading a section of a hardware description language describing a portion of a chip design;
- and
- generating an alternative programming language subroutine from the section of hardware description language read for modeling the behavior of the hardware description language;
- wherein said generating an alternative programming language subroutine comprises:
- flattening said read section of hardware description language;
- forming a set of unordered pairs of assignments using behavioral elaboration;
- sorting said set of unordered pairs into an ordered set of sequential assignments and an ordered set of combinatorial assignments;
- and
- converting said sets of unordered pairs into an alternative programming language.
A method for converting Verilog into C or C++ using a compiler, comprising:
- reading a Verilog section with said compiler;
- flattening said Verilog section into a single module;
- converting said module into a set of pairs of unordered assignments;
- sorting said set of pairs of unordered assignments into ordered sequential groups of assignments and ordered combinatorial groups of assignments;
- and
- converting said ordered sequential groups of assignments and ordered combinatorial groups of assignments into a C or C++ programming language.
Dependencies are inferred from the claim text.