Method and system for finding static NAND and NOR gates within a circuit and identifying the constituent FETs each gate

A computer-readable medium having computer-executable instructions for performing a method for identifying logic gates in an circuit design, the method comprising:

• identifying directly-connected FETs of a first type connected to an output node and having gate signals;
• identifying branch FETs of a second type connected to the output node and having gate signals;
• for at least one of the identified FETS, storing a name of the FET and a name of a gate signal that corresponds to the FET;
• and
• comparing the directly-connected FET gate signals to the branch FET gate signals to identify the logic gates, wherein the step of comparing comprises cross-referencing names of the directly-connected FET gate signals or the branch FET gate signals with the name of the stored gate signal.

A computer system for identifying constituent FETs of a NAND or a NOR gate in a circuit design comprising:

• a storage medium;
• and
• a processor for executing a software program stored on the storage medium for identifying the constituent FETs, the software program comprising a set of instructions for:
• identifying directly-connected FETs of a first type connected to an output node;
• identifying branch FETs of a second type connected to the output node and having gate signals;
• for at least one of the identified FETS, storing a name of the FET and a name of a gate signal that corresponds to the FET;
• and
• comparing the directly-connected FET gate signals to the branch FET gate signals to identify the logic gates, wherein the step of comparing comprises cross-referencing names of the directly-connected FET gate signals or the branch FET gate signals with the name of the stored gate signal.