Rate (M/N) code encoder, detector, and decoder for control data

A method of generating a sequence of blocks of N symbol bits from a sequence of channel samples, the sequence of channel samples representing a sequence of control data and received from a medium, the method comprising the steps of:

• (a) receiving successive portions of the sequence of channel samples as transitions between sequential states of a trellis, wherein:
• the sequence of channel samples corresponds to the sequence of blocks of N symbol bits, each block of N symbol bits is formed from a block of M data bits of control data in accordance with a rate (M/N) code, M being an integer greater than 1 and N being an integer greater than M;
• (b) synchronizing a set of trellis phases and a set of forcing phases to the sequential states, the set of trellis phases corresponding to a block of N channel samples;
• and
• (c) determining, in accordance with a maximum-likelihood detection algorithm, a path through states of the set of trellis phases, the path of states corresponding to a received block of N symbol bits, wherein:
• for each trellis phase, a corresponding forcing phase provides, if necessary, a forced decision to the maximum-likelihood detection algorithm for a transition between states in the trellis, the forced decision based on a constraint of the rate (M/N) code.

An integrated circuit having a detector circuit for generating a sequence of blocks of N symbol bits from a sequence of channel samples, the sequence of channel samples representing a sequence of control data in a signal received from a medium, the detector circuit comprising:

• a processor for implementing a trellis of a maximum-likelihood detection algorithm by receiving successive portions of the sequence of channel samples as transitions between sequential states of a trellis, the sequence of channel samples corresponding to the sequence of blocks of N symbol bits, each block of N symbol bits being formed from a block of M data bits of control data in accordance with a rate (M/N) code, M being an integer greater than 1 and N being an integer greater than M;
• wherein the processor:
• (1) synchronizes a set of trellis phases to the sequential states, the set of trellis phases corresponding to a block of N channel samples, and
• (2) determines, in accordance with the maximum-likelihood detection algorithm, a path through states of the set of trellis phases, the path of states corresponding to a received block of N symbol bits;
• and
• a forcing logic circuit for generating a set of forcing phases synchronized to the set of trellis phases and to the sequential states,
• wherein for each trellis phase, a corresponding forcing phase of the forcing logic circuit provides the processor, if necessary, a forced decision to the maximum-likelihood detection algorithm for a transition between states in the trellis, the forced decision based on a constraint of the rate (M/N) code.

A computer-readable medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by a processor, cause the processor to implement a method of generating a sequence of blocks of N symbol bits from a sequence of channel samples representing information and read from a medium, the method comprising the steps of:

• (a) receiving successive portions of the sequence of channel samples as transitions between sequential states of a trellis, wherein:
• the sequence of channel samples corresponds to the sequence of blocks of N symbol bits, each block of N symbol bits is formed from a block of M data bits of control data in accordance with a rate (M/N) code, M being an integer greater than 1 and N being an integer greater than M;
• (b) synchronizing a set of trellis phases and a set of forcing phases to the sequential states, the set of trellis phases corresponding to a block of N channel samples;
• and
• (c) determining, in accordance with a maximum-likelihood detection algorithm, a path through states of the set of trellis phases, the path of states corresponding to a received block of N symbol bits, wherein:
• for each trellis phase, a corresponding forcing phase provides, if necessary, a forced decision to the maximum-likelihood detection algorithm for a transition between states in the trellis, the forced decision based on a constraint of the rate (M/N) code.

A detector circuit for generating a sequence of blocks of N symbol bits from a sequence of channel samples, the sequence of channel samples representing a sequence of control data and read from a medium, the detector circuit comprising:

• a processor for implementing a trellis of a maximum-likelihood detection algorithm by receiving successive portions of the sequence of channel samples as transitions between sequential states of a trellis, the sequence of channel samples corresponding to the sequence of blocks of N symbol bits, each block of N symbol bits being formed from a block of M data bits of control data in accordance with a rate (M/N) code, M being an integer greater than 1 and N being an integer greater than M;
• wherein the processor:
• (1) synchronizes a set of trellis phases to the sequential states, the set of trellis phases corresponding to a block of N channel samples, and
• (2) determines, in accordance with the maximum-likelihood detection algorithm, a path through states of the set of trellis phases, the path of states corresponding to a received block of N symbol bits;
• and
• a forcing logic circuit for generating a set of forcing phases synchronized to the set of trellis phases and to the sequential states, wherein:
• for each trellis phase, a corresponding forcing phase of the forcing logic circuit provides the processor, if necessary, a forced decision to the maximum-likelihood detection algorithm for a transition between states in the trellis, the forced decision based on a constraint of the rate (M/N) code.